公开(公告)号：US07323743B2

公开(公告)日：2008-01-29

申请号：US11603771

申请日：2006-11-22

申请人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

发明人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

摘要： A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

摘要翻译： 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US07135731B2

公开(公告)日：2006-11-14

申请号：US10707396

申请日：2003-12-10

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

摘要： A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

摘要翻译： 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US07005701B2

公开(公告)日：2006-02-28

申请号：US10318551

申请日：2002-12-13

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L29/76 ,  H01L39/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06995061B2

公开(公告)日：2006-02-07

申请号：US10779607

申请日：2004-02-18

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

公开(公告)号：US20050156233A1

公开(公告)日：2005-07-21

申请号：US11076499

申请日：2005-03-09

申请人： Chi-Hui Lin

发明人： Chi-Hui Lin

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

摘要翻译： 堆叠式栅极闪存器件及其制造方法。 层叠栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。

公开(公告)号：US06916715B2

公开(公告)日：2005-07-12

申请号：US10694155

申请日：2003-10-27

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/148

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06847068B2

公开(公告)日：2005-01-25

申请号：US10441801

申请日：2003-05-19

申请人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

发明人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8242

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

公开(公告)号：US06815290B2

公开(公告)日：2004-11-09

申请号：US10457867

申请日：2003-06-10

申请人： Chi-Hui Lin ,  Chung-Lin Huang

发明人： Chi-Hui Lin ,  Chung-Lin Huang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06649473B1

公开(公告)日：2003-11-18

申请号：US10330777

申请日：2002-12-27

申请人： Chi-Hui Lin ,  Chung-Lin Huang

发明人： Chi-Hui Lin ,  Chung-Lin Huang

IPC分类号： H01L21336

CPC分类号： H01L21/28273

摘要： A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

摘要翻译： 一种制造闪存的浮动栅极的方法。 在半导体衬底上形成有源区。 在有源区域中依次形成第一绝缘层，第一导电层和掩模层。 去除掩模层的一部分以形成第一开口。 形成第二导电层以覆盖掩模层和第一开口的底表面和侧壁。 在第二导电层上形成第二绝缘层以填充第一开口。 进行氧化处理，直到与掩模层上的第二绝缘层接触的第二导电层被氧化成第三绝缘层。 去除第二和第三绝缘层以形成第二开口。 第四绝缘层填充在第二开口中。 除去掩蔽层和被第四绝缘层未覆盖的掩蔽层下面的第一导电层。

公开(公告)号：US06475894B1

公开(公告)日：2002-11-05

申请号：US10052622

申请日：2002-01-18

申请人： Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

发明人： Chung-Lin Huang ,  Sheng-Tsung Chen ,  Chi-Hui Lin

IPC分类号： H01L218247

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L27/115

摘要： The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the oxidation process, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay is prevented.

摘要翻译： 本发明提供一种制造闪速存储器的浮动栅极的方法。 首先，在半导体衬底中形成隔离区，并且隔离区的高度高于衬底。 然后形成栅极氧化物层和第一多晶硅层。 第一多晶硅层根据隔离区域的轮廓形成，以在第一多晶硅层中形成凹陷。 牺牲绝缘体填充到凹部中。 然后使用牺牲绝缘体作为硬掩模以自对准方式选择性地去除第一多晶硅层以暴露隔离区域。 在第一多晶硅层的侧壁上形成多晶硅间隔物。 在隔离区域上形成第一掩模层，去除凹槽中的牺牲绝缘体，并且限定浮栅区域。 然后，浮置栅极区域中的第一多晶硅层和多晶硅间隔物的表面被氧化以形成多晶硅氧化物层。 最后，使用多晶硅氧化物层作为掩模，以自对准的方式对下面的第一多晶硅层和多晶硅间隔物进行图案化以形成浮栅。 在氧化过程中，本发明的多晶硅间隔物用作缓冲层，其被氧化并保护浮栅不被氧化。 因此，防止浮动栅极和STI覆盖，以及由覆盖不足引起的电流泄漏。