Invention Grant
- Patent Title: Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
- Patent Title (中): 非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间
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Application No.: US09973131Application Date: 2001-10-09
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Publication No.: US06664191B1Publication Date: 2003-12-16
- Inventor: Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
- Applicant: Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
- Main IPC: H01L21302
- IPC: H01L21302

Abstract:
A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.
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