An information processing equipment designed to support the compatibility of a plurality of clocks such as its internal clock and a clock for external bus interface by using only a single wired-in line for supplying the internal clock; and to perform frequency conversion control only in a logical circuit with the internal-to-external clock frequency ratio being N:1 or N:2 for the clocks, wherein the equipment comprises: a signal generator for supplying a common reference clock to itself and peripheral equipment and generating a reference sync signal from the reference clock to synchronize itself and the peripheral equipment; a signal generator for generating its internal clock from the reference clock; a signal generator for generating timing signals to control the timing of access to the external bus in accordance with an internal-to-peripheral clock frequency ratio; and a bus I/O signal conversion circuit for carrying out data input/output from/to the bus in accordance with generated timing signals.