Input-output circuit cell and semiconductor integrated circuit apparatus
    1.
    发明授权
    Input-output circuit cell and semiconductor integrated circuit apparatus 失效
    输入输出电路单元和半导体集成电路装置

    公开(公告)号:US06355984B2

    公开(公告)日:2002-03-12

    申请号:US09828193

    申请日:2001-04-09

    IPC分类号: H01L2980

    摘要: An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

    摘要翻译: 输入输出电路单元包括形成在半导体芯片上并具有信号端子和电源端子的输入输出电路和连接到输入 - 输出电路的信号和电源端子的多个输入 - 输出凸块 通过布线分别使多个输入输出凸块对应于输入 - 输出电路并且布置在输入 - 输出电路的投影平面中的中心。 因此,输入输出电路配置在半导体芯片上的任意位置。

    Computer system and routing control method

    公开(公告)号:US09612989B2

    公开(公告)日:2017-04-04

    申请号:US13997539

    申请日:2010-12-24

    摘要: The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

    COMPUTER SYSTEM AND ROUTING CONTROL METHOD
    3.
    发明申请
    COMPUTER SYSTEM AND ROUTING CONTROL METHOD 有权
    计算机系统和路由控制方法

    公开(公告)号:US20140006679A1

    公开(公告)日:2014-01-02

    申请号:US13997539

    申请日:2010-12-24

    IPC分类号: G06F13/40

    摘要: The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

    摘要翻译: 本发明消除了使用PCIe交换机的路由控制中总线数量的不足。 系统端口地址(SPA)与目的地总线号相关联,并分配给连接到服务器和设备的端口(外部端口)。 当在外部端口接收到从服务器或设备发送的数据包时,确定与具有数据包的目标总线号码相对应的系统端口地址(SPA),并将SPA作为标签添加到数据包。 此SPA用于路由连接交换机的端口(内部端口)之间发送的数据包。 当分组到达目标服务器或设备连接的外部端口时,具有分组的目的地总线号码用于将数据包发送到连接到外部端口的服务器或设备。

    COMPUTER SYSTEM AND METHOD FOR SIGNAL TRANSMITTING
    4.
    发明申请
    COMPUTER SYSTEM AND METHOD FOR SIGNAL TRANSMITTING 审中-公开
    计算机系统和信号传输方法

    公开(公告)号:US20120191887A1

    公开(公告)日:2012-07-26

    申请号:US13347159

    申请日:2012-01-10

    IPC分类号: G06F13/42

    CPC分类号: G06F13/4282 G06F2213/0026

    摘要: In order to suppress occurrence of a random pattern signal is suppressed without the use of a sideband signal in a long distance data transmission exceeding that defined in a PCIe interface specification, provided is a computer system, including a first component having a transmitting unit which transmits a control signal, a second component having a receiving unit which receives the control signal, a transmission path which connects the first component and the second component along which a signal is transmitted and received, wherein: in case of the transmitting unit of the first component transmits a ternary signal with three states of 0/1/Idle to the receiving unit of the second component, the transmitting unit of the first component substitutes a combination of signals representing 0/1 for a signal representing the Idle state, and transmits the substituted signals instead of the ternary signal to the receiving unit of the second component.

    摘要翻译: 为了抑制随机模式信号的发生,在长距离数据传输中不使用超出PCIe接口规范中规定的边带信号的情况下,提供了一种计算机系统,其包括具有发送单元的第一部件 控制信号,具有接收控制信号的接收单元的第二分量,连接发送和接收信号的第一分量和第二分量的传输路径,其中:在第一分量的发送单元的情况下, 将具有0/1 /空闲三种状态的三态信号发送到第二分量的接收单元,第一分量的发送单元代表表示空闲状态的信号的代表0/1的信号的组合,并且发送取代 信号而不是第三组件的接收单元的三进制信号。

    Semiconductor integrated circuit and method of testing the same
    5.
    发明授权
    Semiconductor integrated circuit and method of testing the same 失效
    半导体集成电路和测试方法相同

    公开(公告)号:US06321355B1

    公开(公告)日:2001-11-20

    申请号:US09204153

    申请日:1998-12-03

    IPC分类号: G01R3128

    CPC分类号: G01R31/318536

    摘要: An LSI having a logic circuit and a test circuit is provided with a first register which is connected between an LSI input/output pin and the logic circuit and has a first input terminal to be outputted from the first register in accordance with a system clock signal and a second input terminal, a second register which has a first input terminal inputted with an output of the first register and a second input terminal inputted with scan-in data and an output of which is connected to the second input terminal of the first register, a selector circuit which is connected to one of the first input terminal of the second register and the second terminal of the first register and selects one of a signal relating to scan-out data and an output signal of the other register so that the selected signal is inputted to the one input terminal, and a third register which receives an output of the second register and provides the received output as scan-out data in accordance with another clock signal. An output of the third register is successively provided to another LSI input/output pin. The selector circuit includes a logic gate circuit inputted with a signal indicative of an LSI test mode and the output signal of the other register.

    摘要翻译: 具有逻辑电路和测试电路的LSI具有连接在LSI输入/输出引脚和逻辑电路之间的第一寄存器,并具有根据系统时钟信号从第一寄存器输出的第一输入端 以及第二输入端子,第二寄存器,其具有输入了第一寄存器的输出的第一输入端子和输入了扫描数据的第二输入端子,其输出端连接到第一寄存器的第二输入端子 选择器电路,其连接到第二寄存器的第一输入端和第一寄存器的第二端之一,并选择与扫描输出数据有关的信号和另一寄存器的输出信号之一,使得所选择的 信号被输入到一个输入端,以及第三寄存器,其接收第二寄存器的输出,并根据另一个时钟信号将接收到的输出提供为扫描数据 l。 第三寄存器的输出依次提供给另一个LSI输入/输出引脚。 选择器电路包括输入了指示LSI测试模式的信号和另一个寄存器的输出信号的逻辑门电路。

    COMPUTER SYSTEM AND METHOD FOR COMMUNICATING DATA BETWEEN COMPUTERS
    6.
    发明申请
    COMPUTER SYSTEM AND METHOD FOR COMMUNICATING DATA BETWEEN COMPUTERS 有权
    计算机系统与计算机之间的通信数据的方法

    公开(公告)号:US20140269754A1

    公开(公告)日:2014-09-18

    申请号:US14360022

    申请日:2012-03-16

    IPC分类号: H04L12/935

    CPC分类号: H04L49/30 G06F13/4022

    摘要: In a computer on the transmission side, an NW driver, which is recognized, by the OS, as an NIC driver, stores data to be transmitted and a destination SPA into a memory, and outputs a transaction layer packet (TLP), which has been generated by a first computer, to a PCIe switch. A first NIC logic of the PCIe switch of the PCIe switch corresponding to the first computer on the transmission side adds a system port address (SPA) to the TLP transferred from the first computer, and transfers the data of the TLP to a port associated with a second NIC logic and having an address indicated by the SPA (destination SPA). The second NIC logic having received the data writes the receive data into a memory of a second computer, on the reception side, which is connected to another PCIe switch where the second NIC logic exists.

    摘要翻译: 在发送侧的计算机中,由OS识别为NIC驱动器的NW驱动器将要发送的数据和目的地SPA存储到存储器中,并且输出具有的交易层分组(TLP) 由第一台计算机生成,到PCIe交换机。 对应于传输侧第一台计算机的PCIe交换机的PCIe交换机的第一个NIC逻辑将从第一台计算机传输的TLP添加系统端口地址(SPA),并将TLP的数据传输到与 第二NIC逻辑并且具有由SPA(目的地SPA)指示的地址。 已经接收到数据的第二NIC逻辑将接收数据写入接收侧的第二计算机的存储器,该第二计算机连接到存在第二NIC逻辑的另一个PCIe交换机。

    Information processing equipment and information processing system
    7.
    发明授权
    Information processing equipment and information processing system 失效
    信息处理设备和信息处理系统

    公开(公告)号:US06675249B2

    公开(公告)日:2004-01-06

    申请号:US09750960

    申请日:2000-12-27

    IPC分类号: G06F1300

    CPC分类号: G06F1/10

    摘要: An information processing equipment designed to support the compatibility of a plurality of clocks such as its internal clock and a clock for external bus interface by using only a single wired-in line for supplying the internal clock; and to perform frequency conversion control only in a logical circuit with the internal-to-external clock frequency ratio being N:1 or N:2 for the clocks, wherein the equipment comprises: a signal generator for supplying a common reference clock to itself and peripheral equipment and generating a reference sync signal from the reference clock to synchronize itself and the peripheral equipment; a signal generator for generating its internal clock from the reference clock; a signal generator for generating timing signals to control the timing of access to the external bus in accordance with an internal-to-peripheral clock frequency ratio; and a bus I/O signal conversion circuit for carrying out data input/output from/to the bus in accordance with generated timing signals.

    摘要翻译: 一种信息处理设备,其设计为仅通过仅使用单个有线输入线来提供内部时钟来支持诸如其内部时钟和外部总线接口的时钟的多个时钟的兼容性; 并且仅在时钟的内部对外部时钟频率比为N:1或N:2的逻辑电路中进行变频控制,其中,所述设备包括:信号发生器,用于向其自身提供公共参考时钟;以及 周边设备,并从参考时钟产生参考同步信号,以使其自身和外围设备同步; 用于从参考时钟产生其内部时钟的信号发生器; 信号发生器,用于产生定时信号,以根据内部至外围时钟频率比来控制对外部总线的接入定时; 以及总线I / O信号转换电路,用于根据产生的定时信号从总线执行数据输入/输出。

    Fault detecting apparatus for a microprocessor system
    9.
    发明授权
    Fault detecting apparatus for a microprocessor system 失效
    微处理器系统的故障检测装置

    公开(公告)号:US5640508A

    公开(公告)日:1997-06-17

    申请号:US327871

    申请日:1994-10-24

    IPC分类号: G06F11/18 G06F11/00 G06F11/16

    摘要: A fault detecting apparatus includes first and second processors having an internal state generating logic unit for exclusive-ORing the operation outputs and generating an internal state signal of the first and second processors, and a state comparator unit included in the first and second processors for comparing the internal state signals of the first and second processors. When the internal state signals fail to coincide with each other, the state comparator unit decides on an error of at least one of the first and second processors.

    摘要翻译: 一种故障检测装置,包括具有内部状态产生逻辑单元的第一和第二处理器,用于对操作输出进行异或运算并产生第一和第二处理器的内部状态信号;以及包括在第一和第二处理器中的状态比较器单元,用于比较 第一和第二处理器的内部状态信号。 当内部状态信号彼此不一致时,状态比较器单元决定第一和第二处理器中的至少一个处理器的错误。

    Invalidation of entries in a translation table by providing the machine
a unique identification thereby disallowing a match and rendering the
entries invalid
    10.
    发明授权
    Invalidation of entries in a translation table by providing the machine a unique identification thereby disallowing a match and rendering the entries invalid 失效
    通过为机器提供唯一的标识,从而不允许匹配并使条目无效,使转换表中条目无效

    公开(公告)号:US5317710A

    公开(公告)日:1994-05-31

    申请号:US681446

    申请日:1991-04-03

    CPC分类号: G06F12/1036

    摘要: A virtual computer system having a translation lookaside buffer which converts a virtual address to a real address comprises a register (VMNR) for storing the identification number (VMID) of a currently running virtual machine, the translation lookaside buffer having a bit for holding the VMID and a comparison circuit which compares the VMID held in the bit with the VMID provided by the VMNR and predicates the success of conversion from a virtual address to a real address on the basis of a matching result of comparison, a management table for holding data indicative of VMIDs used to define virtual machines which have run up to the current time point, and a control circuit which, when an invalidation command for the translation lookaside buffer is issued during a run of a virtual machine, selects an unused VMID as first information for defining the running virtual machine on the basis of the contents of the management table and sets the selected VMID in the VMNR.

    摘要翻译: 具有将虚拟地址转换为实际地址的翻译后备缓冲器的虚拟计算机系统包括用于存储当前正在运行的虚拟机的标识号(VMID)的寄存器(VMNR),具有用于保存VMID的位的转换后备缓冲器 以及比较电路,其将保持在该比特中的VMID与由VMNR提供的VMID进行比较,并且基于比较的匹配结果来确定从虚拟地址到真实地址的转换的成功;用于保存数据的管理表 用于定义已经运行到当前时间点的虚拟机的VMID;以及控制电路,当在虚拟机的运行期间发出用于翻译后备缓冲器的无效命令时,选择未使用的VMID作为第一信息, 根据管理表的内容定义正在运行的虚拟机,并在VMNR中设置选定的VMID。