A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The semiconductor structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain. The system also includes a processor and a bus connecting the processor and the memory device.