发明授权
- 专利标题: Circuit board design aiding
- 专利标题(中): 电路板设计辅助
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申请号: US09241946申请日: 1999-02-01
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公开(公告)号: US06691296B1公开(公告)日: 2004-02-10
- 发明人: Takeshi Nakayama , Yukihiro Fukumoto , Yoshiyuki Saito , Hirokazu Uemura
- 申请人: Takeshi Nakayama , Yukihiro Fukumoto , Yoshiyuki Saito , Hirokazu Uemura
- 优先权: JP10-021089 19980202; JP10-364143 19981222
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.
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