发明授权
US06693035B1 Methods to control film removal rates for improved polishing in metal CMP
失效
控制膜去除速率以改善金属CMP抛光的方法
- 专利标题: Methods to control film removal rates for improved polishing in metal CMP
- 专利标题(中): 控制膜去除速率以改善金属CMP抛光的方法
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申请号: US09420682申请日: 1999-10-19
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公开(公告)号: US06693035B1公开(公告)日: 2004-02-17
- 发明人: Vikas Sachan , Peter A. Burke , Elizabeth A. (Kegerise) Langlois , Keith G. Pierce
- 申请人: Vikas Sachan , Peter A. Burke , Elizabeth A. (Kegerise) Langlois , Keith G. Pierce
- 主分类号: H01L21302
- IPC分类号: H01L21302
摘要:
A method for chemical mechanical planarization of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer using a two-step polishing process is provided. In the first step, the conducting metal overburden is substantially removed with little removal of the barrier or liner layer or the underlying dielectric structure. In the second step, the barrier layer is removed with little removal of the underlying dielectric layer. Five different methods and associated slurry compositions are described for the second polishing step, each adjusted to the state of the wafer following the first step of polishing. By using the appropriate method, the integrity of the remaining semiconductor structure can be substantially retained.
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