A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably >1.3:1:1.