公开(公告)号：US08968485B2

公开(公告)日：2015-03-03

申请号：US13251064

申请日：2011-09-30

Applicant: Arjun Mendiratta ,  Cheng-Yu Lin ,  David Mui

Inventor： Arjun Mendiratta ,  Cheng-Yu Lin ,  David Mui

IPC: B08B3/00 ,  B08B1/02 ,  B08B3/04 ,  H01L21/02 ,  H01L21/67

CPC classification number: B08B1/02 ,  B08B3/04 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/6704 ,  H01L21/67051

Abstract: An apparatus for processing a substrate, comprising: a process chamber having a track; a carrier connected to the track; upper and lower proximity heads in the chamber and positioned along the path, the proximity heads having opposing faces that define a gap in which a meniscus of fluid is formed, the path being defined along the gap between the opposing faces; a first pre-wet dispenser and a second pre-wet dispenser disposed along side of the upper proximity head and directed toward the path; a drive for moving each of the pre-wet dispensers between a center position along the length of the upper proximity head and opposite outer positions near outer ends of the upper proximity head; and a pre-wet controller for causing the drive to move each of the first and second pre-wet dispensers based on a position of the carrier when moved under the first and second pre-wet dispensers.

Abstract translation: 一种用于处理衬底的设备，包括：具有轨道的处理室; 连接到轨道的载体; 所述腔室中的上和下邻近头部沿所述路径定位，所述邻近头部具有限定形成有液体弯液面的间隙的相对面，所述路径沿着相对面之间的间隙限定; 第一预湿式分配器和第二预湿式分配器，其设置在上接近头部的侧面并且朝向路径; 驱动器，用于在沿着上邻近头部的长度的中心位置和靠近上接近头部的外端的相对的外部位置之间移动每个预湿式分配器; 以及预湿式控制器，用于当所述第一和第二预湿式分配器下移动时，使得所述驱动器基于所述载体的位置移动所述第一和第二预湿式分配器中的每一个。

公开(公告)号：US08480809B2

公开(公告)日：2013-07-09

申请号：US13351217

申请日：2012-01-16

Applicant: Ji Zhu ,  Arjun Mendiratta ,  David Mui

Inventor： Ji Zhu ,  Arjun Mendiratta ,  David Mui

IPC: B08B3/00 ,  C11D11/00

CPC classification number: B08B3/02 ,  C11D3/2079 ,  C11D3/222 ,  C11D3/37 ,  C11D3/3707 ,  C11D3/3723 ,  C11D3/3753 ,  C11D3/3765 ,  C11D3/3773 ,  C11D3/378 ,  C11D3/43 ,  C11D7/265 ,  C11D7/268 ,  C11D7/5004 ,  C11D11/0047 ,  C11D17/0013 ,  C11D17/003 ,  Y10S134/902

Abstract: A method is provided for receiving the wafer on a support, the support being configured for movement along a direction. While moving the wafer, dispensing a cleaning material to clean contaminants from the surface of the wafer, the dispensing applied as a film over a diameter length of the wafer. The cleaning material contains a cleaning liquid, a plurality of solid components, and polymers of a polymeric compound. Each of the plurality of solid components and polymers being greater than zero and less than 3% of the cleaning material, and wherein the polymers become soluble in the cleaning liquid and the solubilized polymers having long polymer chains that capture and entrap solid components and contaminants in the cleaning liquid. Then, rinsing the film off of the wafer with a rinsing meniscus. The rinsing meniscus applied along the diameter length of the wafer and the film is rinsed after the dispensing.

Abstract translation: 提供了一种用于在支撑件上接收晶片的方法，所述支撑件被配置为沿着方向移动。 在移动晶片时，分配清洁材料以清洁来自晶片表面的污染物，分配作为薄膜施加在晶片的直径长度上。 清洁材料包含清洁液体，多种固体组分和聚合物的聚合物。 多个固体组分和聚合物中的每一种都大于零且小于洗涤材料的3％，并且其中聚合物变得可溶于清洁液体，并且具有长的聚合物链的溶解聚合物捕获并捕获固体组分和污染物 清洗液。 然后，用冲洗弯液面从晶片上冲洗薄膜。 沿着晶片的直径长度施加的冲洗弯月面，并且在分配之后冲洗薄膜。

公开(公告)号：US20120159125A1

公开(公告)日：2012-06-21

申请号：US13408739

申请日：2012-02-29

Applicant: Ronald D. Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald D. Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/38 ,  G06F9/312

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

Abstract translation: 一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 指令在循环周期长度存储在修改后的指令缓冲区中。 处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

公开(公告)号：US20100108093A1

公开(公告)日：2010-05-06

申请号：US12262094

申请日：2008-10-30

Applicant: Grant Peng ,  David Mui ,  Shih-Chung Kon

Inventor： Grant Peng ,  David Mui ,  Shih-Chung Kon

IPC: B08B3/12

CPC classification number: H01L21/67051

Abstract: A method for cleaning a substrate is provided that includes applying a liquid medium to a surface of the substrate such that the liquid medium substantially covers a portion of the substrate that is being cleaned. One or more transducers are used to generate acoustic energy. The generated acoustic energy is applied to the substrate and the liquid medium meniscus such that the applied acoustic energy to the liquid medium prevents cavitation within the liquid medium. The acoustic energy applied to the substrate provides maximum acoustic wave displacement to acoustic waves introduced into the liquid medium. The acoustic energy introduced into the substrate and the liquid medium enables dislodging of the particle contaminant from the surface of the substrate. The dislodged particle contaminants become entrapped within the liquid medium and are carried away from the surface of the substrate by the liquid medium.

Abstract translation: 提供一种用于清洁衬底的方法，其包括将液体介质施加到衬底的表面，使得液体介质基本上覆盖正被清洁的衬底的一部分。 使用一个或多个换能器来产生声能。 产生的声能被施加到衬底和液体介质弯液面，使得向液体介质施加的声能防止液体介质内的气蚀。 施加到衬底的声能提供了引入到液体介质中的声波的最大声波位移。 引入到基底和液体介质中的声能使得能够从基底表面移除颗粒污染物。 脱落的颗粒污染物被捕获在液体介质中，并通过液体介质从基板的表面带走。

公开(公告)号：US20090113191A1

公开(公告)日：2009-04-30

申请号：US11923709

申请日：2007-10-25

Applicant: Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/30

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

Abstract translation: 一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 指令在循环周期长度存储在修改后的指令缓冲区中。 处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

公开(公告)号：US20070202706A1

公开(公告)日：2007-08-30

申请号：US11743882

申请日：2007-05-03

Applicant: David Mui ,  Wei Liu

Inventor： David Mui ,  Wei Liu

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L21/32137

Abstract: A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

公开(公告)号：US07250373B2

公开(公告)日：2007-07-31

申请号：US10927807

申请日：2004-08-27

Applicant: David Mui ,  Wei Liu

Inventor： David Mui ,  Wei Liu

IPC: H01L21/302

CPC classification number: H01L21/32137

Abstract: A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

Abstract translation: 一种用于使用包括钝化气体的气体混合物在衬底上蚀刻具有高均匀度横向蚀刻速率的材料层的方法和装置。 钝化气体被提供到衬底的周边区域以钝化被蚀刻的结构的侧壁。

公开(公告)号：US06911399B2

公开(公告)日：2005-06-28

申请号：US10665934

申请日：2003-09-19

Applicant: Wei Liu ,  David Mui

Inventor： Wei Liu ,  David Mui

IPC: H01L21/3065 ,  G03F7/40 ,  H01L21/027 ,  H01L21/311 ,  H01L21/302

CPC classification number: H01L21/31138 ,  G03F7/40 ,  H01L21/0274

Abstract: A method for trimming photoresist features on a semiconductor substrate in a processing system. The method utilizes a process gas mixture comprising a hydrocarbon gas, an oxygen gas and an inert gas. The critical dimension (CD) microloading of the dense and the isolated regions can be eliminated and the photoresist trimming rate can also be reduced to enable better critical dimension (CD) control.

公开(公告)号：US06703315B2

公开(公告)日：2004-03-09

申请号：US10165894

申请日：2002-06-10

Applicant: Wei Liu ,  David Mui

Inventor： Wei Liu ,  David Mui

IPC: H01L21302

CPC classification number: H01L27/10861 ,  H01L21/76232

Abstract: A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably >1.3:1:1.

Abstract translation: 一种在沟槽电容器结构内形成浅沟槽的方法。 该方法可以用于例如DRAM器件的构造。 该方法包括：（1）提供一种沟槽电容器结构，其包括（a）具有上表面和下表面的硅衬底; （b）从上表面延伸到硅衬底中的第一和第二沟槽; （c）在第一和第二沟槽的至少一部分内衬的第一和第二氧化物区域; 和（d）至少部分地填充氧化物衬里的第一和第二沟槽的第一和第二多晶硅区域; 和（2）从结构的上表面形成浅沟槽，浅沟槽具有基本平坦的沟槽底部，其与硅衬底，第一氧化物区域，第二氧化物区域，第一多晶硅区域的部分形成界面 和第二多晶硅区域，所述浅沟槽通过包括（a）第一等离子体蚀刻步骤形成的工艺，所述第一等离子体蚀刻步骤具有氧化物：硅：多晶硅选择性<1：1：1，和（b）第二等离子体蚀刻步骤，其具有氧化物 硅：多晶硅选择性> 1：1，更优选> 1.3:1:1。

公开(公告)号：US06238844B1

公开(公告)日：2001-05-29

申请号：US09243207

申请日：1999-02-02

Applicant: Olivier Joubert ,  Cedric Monget ,  Timothy Weidman ,  Dian Sugiarto ,  David Mui

Inventor： Olivier Joubert ,  Cedric Monget ,  Timothy Weidman ,  Dian Sugiarto ,  David Mui

IPC: G03F7075

CPC classification number: G03F7/167 ,  G03F7/075 ,  G03F7/095 ,  G03F7/36 ,  H01L21/31133 ,  H01L21/312

Abstract: A process for patterning a feature on a substrate using; a plasma polymerized methylsilane (PPMS) photoresist layer or similar organosilicon film. The process includes the step of depositing a PPMS film having upper and lower strata such that the upper stratum is more photosensitive to ultraviolet radiation than is the lower stratum. In one embodiment, the upper and lower strata are formed in a multistep deposition process that, preferably, takes place in a single deposition chamber. In another embodiment, the upper and lower strata are formed by a process in which deposition parameters are modified to deposit a PPMS layer having a photosensitivity gradient between the upper and lower strata. In still another embodiment, various intermediate strata are formed. Preferably, each intermediate stratums has a photosensitivity that is higher than the stratum directly beneath it. Also disclosed is a process for etching a PPMS layer that increases the etch selectivity of PPMS relative to PPMSO from an initial low etch selectivity to a higher etch selectivity at a later stage of the etching process. In one currently preferred embodiment, the etch selectivity used during a first etching step of the process is less than 4:1 and the etch selectivity used during a second etching step, subsequent to the first step, is greater than 5:1. In an even more preferred embodiment, the etch selectivity of the first step is between 2-3:1 and the etch selectivity of the second step is greater than 8:1. Optionally, a third etching step, performed between the first and second etching steps may be employed where the etch selectivity is between 3-8:1.

Abstract translation: 用于使用基板上的特征图案化的工艺; 等离子体聚合甲基硅烷（PPMS）光致抗蚀剂层或类似的有机硅膜。 该方法包括沉积具有上层和下层的PPMS膜的步骤，使得上层对紫外线辐射比下层更光敏。 在一个实施例中，上层和下层以多步沉积工艺形成，优选在单个沉积室中进行。 在另一个实施方案中，上层和下层通过其中沉积参数被修饰以沉积在上层和下层之间具有光敏度梯度的PPMS层的方法形成。 在另一个实施例中，形成各种中间层。 优选地，每个中间层具有高于其正下方的层的光敏性。还公开了一种用于蚀刻PPMS层的方法，其将PPMS相对于PPMSO的蚀刻选择性从初始低蚀刻选择性增加到较高的蚀刻选择性 蚀刻过程的后期阶段。 在一个当前优选的实施方案中，在该方法的第一蚀刻步骤期间使用的蚀刻选择性小于4:1，并且在第一步骤之后的第二蚀刻步骤期间使用的蚀刻选择性大于5:1。 在甚至更优选的实施方案中，第一步骤的蚀刻选择性在2-3:1之间，并且第二步骤的蚀刻选择性大于8:1。 可选地，可以采用在第一和第二蚀刻步骤之间执行的第三蚀刻步骤，其中蚀刻选择性在3-8:1之间。