发明授权
- 专利标题: Power on reset circuit
- 专利标题(中): 上电复位电路
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申请号: US10406312申请日: 2003-04-04
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公开(公告)号: US06710634B2公开(公告)日: 2004-03-23
- 发明人: Shigeki Ohbayashi , Tadayuki Shimizu
- 申请人: Shigeki Ohbayashi , Tadayuki Shimizu
- 优先权: JP2000-090660 20000329; JP2000-290423 20000925
- 主分类号: H03L700
- IPC分类号: H03L700
摘要:
In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.
公开/授权文献
- US20030201807A1 Power on reset circuit 公开/授权日:2003-10-30
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