公开(公告)号：US06584013B2

公开(公告)日：2003-06-24

申请号：US09982792

申请日：2001-10-22

申请人： Minoru Senda ,  Shinichi Kobayashi ,  Masaki Tsukude ,  Hirotoshi Sato ,  Tadayuki Shimizu

发明人： Minoru Senda ,  Shinichi Kobayashi ,  Masaki Tsukude ,  Hirotoshi Sato ,  Tadayuki Shimizu

IPC分类号： G11C1134

CPC分类号： G11C11/005

摘要： A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

公开(公告)号：US06416331B1

公开(公告)日：2002-07-09

申请号：US09644831

申请日：2000-08-24

申请人： Tadayuki Shimizu

发明人： Tadayuki Shimizu

IPC分类号： H01R1200

CPC分类号： H01R13/2471 ,  H01L2224/16225 ,  H01R12/52 ,  H05K7/1069 ,  Y10S439/937

摘要： An IC socket that can improve the efficiency of the lead replacement process and a semiconductor device having such an IC socket are provided. The IC socket is removably mounted on a circuit substrate, and includes a plurality of linear lead members, a lead module, and a socket base body. The lead module is replaceable and holds lead members of each group of a plurality of groups into which the plurality of lead members are divided. The lead module is provided in plurality to hold each of the plurality of groups. The socket base body is placed between the circuit substrate and the lead module and determines the position of the lead module on the circuit substrate.

摘要翻译： 提供了可以提高引线置换处理的效率的IC插座和具有这种IC插座的半导体器件。 IC插座可移除地安装在电路基板上，并且包括多个线性引线构件，引线模块和插座基体。 引线模块是可替换的，并且保持多个引线构件被划分成多个组的每个组的引导构件。 多个引线模块被设置成保持多个组中的每一个。 插座基体放置在电路基板和引线模块之间，并确定引线模块在电路基板上的位置。

公开(公告)号：US5398943A

公开(公告)日：1995-03-21

申请号：US975430

申请日：1992-11-12

申请人： Tadayuki Shimizu ,  Toshihiko Fuse ,  Eiji Okumachi

发明人： Tadayuki Shimizu ,  Toshihiko Fuse ,  Eiji Okumachi

IPC分类号： F16J15/34

CPC分类号： F16J15/3412

摘要： A seal device of the non-contact type having seal faces formed by those end faces of a rotating seal ring and a stationary ring which are perpendicular to axes of the two rings, and also having dynamic pressure generating grooves formed in one of the seal faces at a certain interval in the circumferential direction of the seal face each groove having a first spiral groove portion and a second terminal portion being formed continuous from the front end of each of the first spiral groove portions, extending along the circumferential direction of the seal face but across its corresponding first spiral groove portion, and provided with a closed front end. The seal device can be used at high speed and under high pressure and it can correct the tilting of its seal faces, which is caused by pressure and heat added, to prevent them from being contacted with each other. Even when the difference of pressures added to them changes, the seal device can keep them parallel to each other to reduce the amount of liquid leaked to a greater extent.

摘要翻译： 一种非接触式密封装置，其具有与两个环的轴线垂直的旋转密封环和固定环的端面形成的密封面，并且还具有形成在一个密封面中的动压力产生槽 在密封面的圆周方向上一定间隔，每个凹槽具有第一螺旋槽部分和第二端子部分，其从每个第一螺旋槽部分的前端连续形成，沿着密封面的圆周方向延伸 而是穿过其对应的第一螺旋槽部分，并设置有封闭的前端。 密封装置可以在高速和高压下使用，并且可以校正由加压和加热引起的密封面的倾斜，以防止它们彼此接触。 即使当加到其上的压力差变化时，密封装置也可以保持它们彼此平行以减少泄漏的液体量。

公开(公告)号：US4284445A

公开(公告)日：1981-08-18

申请号：US38134

申请日：1979-05-11

申请人： Tadayuki Shimizu

发明人： Tadayuki Shimizu

IPC分类号： B31F1/24 ,  B31F1/28 ,  G05G15/00 ,  B31F5/04

CPC分类号： B31F1/2831 ,  Y10T156/1016

摘要： An apparatus for detecting the correct timing of lot changing in a corrugator. The sum of a finished extent, which is the product of a specified cut length and the number of cut pieces excluding rejected cut pieces, and the residual quantity of a single-faced or double-faced corrugated board on the production line is subtracted from a lot size or length which is the product of the specified cut length and a specified number of cut pieces, to obtain a residual lot length, and this computation is successively performed at predetermined time intervals. The amount of raw material board fed is successively subtracted from the residual lot length, so that when the difference is reduced to zero, it is an indication of the desired lot changing timing.

摘要翻译： 一种用于检测瓦楞纸机中批次更换正确时间的装置。 将生产线上的单面或双面瓦楞纸板的剩余量从指定切割长度的产品和不包括拒收切割件的切割件数量的总和减去 批量大小或长度，其是指定切割长度和指定数量的切割片的乘积，以获得残余批次长度，并且以预定时间间隔连续执行该计算。 从剩余批次长度连续减去原料板的供给量，从而当差值减小到零时，表示期望的批量变更时间。

公开(公告)号：US08826856B2

公开(公告)日：2014-09-09

申请号：US13058557

申请日：2009-08-17

申请人： Ekishu Nagae ,  Yousong Jiang ,  Ichiro Shiono ,  Tadayuki Shimizu ,  Tatsuya Hayashi ,  Makoto Furukawa ,  Takanori Murata

发明人： Ekishu Nagae ,  Yousong Jiang ,  Ichiro Shiono ,  Tadayuki Shimizu ,  Tatsuya Hayashi ,  Makoto Furukawa ,  Takanori Murata

IPC分类号： C23C16/00 ,  C23C16/50 ,  C23C14/22 ,  C23C14/10 ,  C23C14/08

CPC分类号： C23C14/22 ,  C23C14/083 ,  C23C14/10 ,  C23C14/221 ,  C23C14/225 ,  H01J2237/0041 ,  H01J2237/3132

摘要： An optical thin-film vapor deposition apparatus and method are capable of producing an optical thin-film by vapor depositing a vapor deposition substance onto substrates (14) within a vacuum vessel (10). A dome shaped holder (12) is disposed within the vacuum vessel (10) and holds the substrates (14). A drive rotates the dome shaped holder (12). A vapor depositing source (34) is disposed oppositely to the substrates (14). An ion source (38) irradiates ions to the substrates (14). A neutralizer (40) irradiates electrons to the substrates (14). The ion source (38) is disposed at an angle between an axis, along which ions are irradiated from the ion source (38), and a line perpendicular to a surface of each of the substrates (14). The angle is between 8° inclusive and 40° inclusive. A ratio of a distance in a vertical direction between (i) a center of rotational axis of the dome shaped holder (12), and (ii) a center of the ion source (38), relative to a diameter of the dome shaped holder (12), is between 0.5 inclusive and 1.2 inclusive.

摘要翻译： 光学薄膜蒸镀装置和方法能够通过将气相沉积物质蒸镀在真空容器（10）内的基板（14）上来制造光学薄膜。 圆顶形保持器（12）设置在真空容器（10）内并保持基板（14）。 驱动器旋转圆顶形保持器（12）。 气相沉积源（34）与衬底（14）相对设置。 离子源（38）将离子照射到衬底（14）上。 中和器（40）将电子照射到衬底（14）上。 离子源（38）以垂直于每个基板（14）的表面的线与离子源（38）照射的轴线之间成角度地设置。 角度介于8°至40°之间。 （i）圆顶状保持器（12）的旋转轴的中心与（ii）离子源（38）的中心之间的垂直方向上的距离相对于圆顶状保持器的直径的比例 （12），介于0.5和0.5之间。

公开(公告)号：US06798236B2

公开(公告)日：2004-09-28

申请号：US10271799

申请日：2002-10-17

申请人： Tadayuki Shimizu ,  Takafumi Takatsuka ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Takafumi Takatsuka ,  Masaki Tsukude

IPC分类号： H03K19003

CPC分类号： H03K19/0016 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.

摘要翻译： 一种半导体集成电路，其从外部提供第一电源电压和第二电源电压，以便操作并入的电路，并且在输出端子处输出数据，包括执行用于输入信号的预定功能的内部电路 输出电路，其包括用于将来自内部电路的信号转换为输出信号的第一电路和包含最终级缓冲电路的第二电路，其根据来自第一电路的信号将数据输出到输出端; 以及将提供给第二电路的电源电压切换到第一电源电压或第二电源电压的开关电路。 通过减小第一电源电压获得的电压被提供给内部电路。 第一电源电压被提供给第一电路。

公开(公告)号：US06469552B2

公开(公告)日：2002-10-22

申请号：US09784142

申请日：2001-02-16

申请人： Shigeki Ohbayashi ,  Tadayuki Shimizu

发明人： Shigeki Ohbayashi ,  Tadayuki Shimizu

IPC分类号： H03L700

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

摘要翻译： 在上电复位（POR）电路中，当电源接通时，反相器的输出信号达到H电平，并且N沟道MOS晶体管导通。 逆变器的输入节点的电位变为电源电压除以P沟道MOS晶体管的导电电阻值R1和N沟道MOS晶体管的导电电阻值R2的电位。 假设逆变器的阈值电压为0.8V，R1：R2 = 2：3，则信号POR＃反相时的电源电压Vres为1.33V。因此，该POR电路可以可靠地利用 在设计为使用具有阈值电压为0.8V的MOS晶体管的1.5V工作的产品中。

公开(公告)号：US06710634B2

公开(公告)日：2004-03-23

申请号：US10406312

申请日：2003-04-04

申请人： Shigeki Ohbayashi ,  Tadayuki Shimizu

发明人： Shigeki Ohbayashi ,  Tadayuki Shimizu

IPC分类号： H03L700

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

摘要翻译： 在上电复位（POR）电路中，当电源接通时，反相器的输出信号达到H电平，并且N沟道MOS晶体管导通。 逆变器的输入节点的电位变为电源电压除以P沟道MOS晶体管的导电电阻值R1和N沟道MOS晶体管的导电电阻值R2的电位。 假设逆变器的阈值电压为0.8V，R1：R2 = 2：3，则信号POR＃反相时的电源电压Vres为1.33V。因此，该POR电路可以可靠地利用 在设计为使用具有阈值电压为0.8V的MOS晶体管的1.5V工作的产品中。

公开(公告)号：US06556485B2

公开(公告)日：2003-04-29

申请号：US09972242

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C7/1051

摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

公开(公告)号：US06269462B1

公开(公告)日：2001-07-31

申请号：US09192460

申请日：1998-11-16

申请人： Tadayuki Shimizu ,  Kunihiko Kozaru

发明人： Tadayuki Shimizu ,  Kunihiko Kozaru

IPC分类号： G01R3128

CPC分类号： G11C7/1057 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/32

摘要： A semiconductor device includes a sense amplifier which becomes able to amplify a signal when receiving a read enable signal; a delay unit which can provide a plurality of transmission paths having different delay times and which propagates the read enable signal through a transmission path corresponding to a selection signal among the plurality of transmission paths; a selection signal generation circuit capable of generating the plurality of selection signals; and a JTAG boundary scan test circuit which brings the selection signal generation circuit into operation in accordance with a instruction.

摘要翻译： 半导体器件包括读出放大器，当接收到读使能信号时能够放大信号; 延迟单元，其可以提供具有不同延迟时间的多个传输路径，并且通过与所述多个传输路径中的选择信号相对应的传输路径传播所述读使能信号; 能够产生多个选择信号的选择信号发生电路; 以及根据指令使选择信号生成电路工作的JTAG边界扫描测试电路。