公开(公告)号：US06710634B2

公开(公告)日：2004-03-23

申请号：US10406312

申请日：2003-04-04

申请人： Shigeki Ohbayashi ,  Tadayuki Shimizu

发明人： Shigeki Ohbayashi ,  Tadayuki Shimizu

IPC分类号： H03L700

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

摘要翻译： 在上电复位（POR）电路中，当电源接通时，反相器的输出信号达到H电平，并且N沟道MOS晶体管导通。 逆变器的输入节点的电位变为电源电压除以P沟道MOS晶体管的导电电阻值R1和N沟道MOS晶体管的导电电阻值R2的电位。 假设逆变器的阈值电压为0.8V，R1：R2 = 2：3，则信号POR＃反相时的电源电压Vres为1.33V。因此，该POR电路可以可靠地利用 在设计为使用具有阈值电压为0.8V的MOS晶体管的1.5V工作的产品中。

公开(公告)号：US06469552B2

公开(公告)日：2002-10-22

申请号：US09784142

申请日：2001-02-16

申请人： Shigeki Ohbayashi ,  Tadayuki Shimizu

发明人： Shigeki Ohbayashi ,  Tadayuki Shimizu

IPC分类号： H03L700

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

摘要翻译： 在上电复位（POR）电路中，当电源接通时，反相器的输出信号达到H电平，并且N沟道MOS晶体管导通。 逆变器的输入节点的电位变为电源电压除以P沟道MOS晶体管的导电电阻值R1和N沟道MOS晶体管的导电电阻值R2的电位。 假设逆变器的阈值电压为0.8V，R1：R2 = 2：3，则信号POR＃反相时的电源电压Vres为1.33V。因此，该POR电路可以可靠地利用 在设计为使用具有阈值电压为0.8V的MOS晶体管的1.5V工作的产品中。

公开(公告)号：US06556058B2

公开(公告)日：2003-04-29

申请号：US10268687

申请日：2002-10-11

申请人： Shigeki Ohbayashi ,  Tadayuki Shimizu

发明人： Shigeki Ohbayashi ,  Tadayuki Shimizu

IPC分类号： H03L700

CPC分类号： H03K3/356008 ,  H03K17/223

摘要： In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

公开(公告)号：US20100265752A1

公开(公告)日：2010-10-21

申请号：US12827668

申请日：2010-06-30

申请人： Hidemoto TOMITA ,  Shigeki Ohbayashi ,  Yoshiyuki Ishigaki

发明人： Hidemoto TOMITA ,  Shigeki Ohbayashi ,  Yoshiyuki Ishigaki

IPC分类号： G11C5/02

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S257/904 ,  H01L2924/00

摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a，5b和第二栅极布线元件 连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。

公开(公告)号：US20060285400A1

公开(公告)日：2006-12-21

申请号：US11451312

申请日：2006-06-13

申请人： Shigeki Ohbayashi

发明人： Shigeki Ohbayashi

IPC分类号： G11C7/10

CPC分类号： G11C11/413

摘要： A supply instruction signal attains the H-level before data is written into a plurality of memory cells. A P-channel MOS transistor is arranged between a power supply node and an input node. The P-channel MOS transistor is turned off to open the input node according to the supply instruction signal. In this case, a write driver discharges electric charges accumulated on the input node and electric charges accumulated on a bit line pair. However, a through-current does not flow from the power supply node to a ground node so that flow of the through-current to a CMOS inverter circuit forming each memory cell can be prevented. Accordingly, such a static semiconductor memory device can be provided that can prevent the flow of the through-current to the CMOS inverter circuit forming each memory cell when simultaneously writing data into the plurality of memory cells.

公开(公告)号：US06741510B2

公开(公告)日：2004-05-25

申请号：US10223326

申请日：2002-08-20

申请人： Shigeki Ohbayashi ,  Yoji Kashihara ,  Takahiro Yokoyama

发明人： Shigeki Ohbayashi ,  Yoji Kashihara ,  Takahiro Yokoyama

IPC分类号： G11C700

CPC分类号： G11C29/18 ,  G11C2029/1202 ,  G11C2029/1802 ,  G11C2029/2602

摘要： A control circuit generates burn-in test signals and a signal on the basis of an address for causing transition of a semiconductor memory device to a burn-in test mode to output the signals to a predecoder. The predecoder outputs signals for selecting even-numbered word lines and signals for causing odd-numbered word lines to be in a non-selected state on the basis of the burn-in test signals at H level and further outputs signals for causing even-numbered word lines to be in a non-selected state and signals for selecting odd-numbered word lines on the basis of the burn-in test signals at H level. As a result, stresses can be effectively applied by the burn-in test.

摘要翻译： 控制电路基于用于使半导体存储器件转变为老化测试模式的地址来产生老化测试信号和信号，以将信号输出到预解码器。 预解码器根据H电平的老化测试信号输出用于选择偶数字线和信号的信号，以使奇数字线处于非选择状态，并且还输出用于使偶数字线 字线处于未选择状态，并且基于H电平上的老化测试信号来选择奇数字线的信号。 因此，通过老化测试可以有效地应用应力。

公开(公告)号：US06452269B1

公开(公告)日：2002-09-17

申请号：US09570440

申请日：2000-05-12

申请人： Shigeki Ohbayashi

发明人： Shigeki Ohbayashi

IPC分类号： H01L2348

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  Y10S257/905 ,  Y10S257/909 ,  H01L2924/00

摘要： A semiconductor integrated circuit according to the present invention comprises a memory array, an input circuit for writing data in the memory array and reading data from the memory array, an output circuit and a package, including 100 pins, storing the memory array, the input circuit and the output circuit. A fourth pin, an eleventh pin, a twentieth pin, a twenty-seventh pin, a fifty-fourth pin, a sixty-first pin, a seventieth pin and a seventy-seventh pin are supplied with the same voltage. The input circuit and the output circuit receive a power supply voltage from different ones of these pins. Thus, a semiconductor integrated circuit resistant against noise and capable of responding to a high operating frequency is provided.

摘要翻译： 根据本发明的半导体集成电路包括存储器阵列，用于在存储器阵列中写入数据并从存储器阵列读取数据的输入电路，包括100个引脚的输出电路和封装，存储存储器阵列，输入 电路和输出电路。 第四针，第十一针，第二十针，第二十七针，第五十四针，第六十一针，七十针和七十七针被提供相同的电压。 输入电路和输出电路从这些引脚中的不同端口接收电源电压。 因此，提供了抗噪声并且能够响应高工作频率的半导体集成电路。

公开(公告)号：US5708802A

公开(公告)日：1998-01-13

申请号：US564651

申请日：1995-11-29

申请人： Chikayoshi Morishima ,  Shigeki Ohbayashi

发明人： Chikayoshi Morishima ,  Shigeki Ohbayashi

IPC分类号： G06F1/08 ,  G06F1/04

CPC分类号： G06F1/08

摘要： To obtain a semiconductor memory device capable of keeping the internal circuit in active state at all times, without increasing the power consumption during normal operation, and not increasing the number of pins. A burn-in clock generating circuit (1) receives an external clock CLK, a mode signal MODE, and an internal clock INTCLK to output a burn-in clock BICLK to a decoder (5). The burn-in clock BICLK becomes a signal equivalent to the internal clock INTCLK when the mode signal MODE is a fixed signal of H or L indicating normal operation, and becomes a fixed signal of H for indicating activation at all times when the mode signal MODE is a clock at half frequency of the external clock CLK.

摘要翻译： 为了获得能够始终保持内部电路处于活动状态的半导体存储器件，而不增加正常操作期间的功耗，并且不增加引脚数。 老化时钟发生电路（1）接收外部时钟CLK，模式信号MODE和内部时钟INTCLK，以将老化时钟BICLK输出到解码器（5）。 当模式信号MODE是指示正常操作的H或L的固定信号时，老化时钟BICLK变为等于内部时钟INTCLK的信号，并且当模式信号MODE 是外部时钟CLK的一半频率的时钟。

公开(公告)号：US5703510A

公开(公告)日：1997-12-30

申请号：US608075

申请日：1996-02-28

申请人： Masayuki Iketani ,  Shigeki Ohbayashi

发明人： Masayuki Iketani ,  Shigeki Ohbayashi

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power on reset circuit includes a transistor connected between a power supply node and a first node, a first capacitor connected between a ground node and a first node, a resistance element connected parallel to the first capacitor, a first CMOS inverter circuit having an input node connected to the first node and an output node connected to the second node, and a second CMOS inverter circuit having an input node connected to the second node and an output node connected to the first node. Preferably, the power on reset circuit further includes a second capacitor connected between the power supply node and the second node. In the power on reset circuit, when the power is turned off, the first capacitor is fully discharged by the resistance element. Therefore, a reset signal for initializing internal circuitry can be surely generated even when the power is again turned on.

摘要翻译： 上电复位电路包括连接在电源节点和第一节点之间的晶体管，连接在接地节点和第一节点之间的第一电容器，与第一电容器并联连接的电阻元件，具有输入端的第一CMOS反相器电路 连接到第一节点的节点和连接到第二节点的输出节点，以及具有连接到第二节点的输入节点和连接到第一节点的输出节点的第二CMOS反相器电路。 优选地，上电复位电路还包括连接在电源节点和第二节点之间的第二电容器。 在上电复位电路中，当电源关闭时，第一电容器被电阻元件完全放电。 因此，即使再次接通电源，也可以可靠地产生用于初始化内部电路的复位信号。

公开(公告)号：US5629900A

公开(公告)日：1997-05-13

申请号：US526247

申请日：1995-09-11

申请人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

发明人： Toshihiko Hirose ,  Shigeki Ohbayashi ,  Setsu Kondo ,  Takashi Hayasaka ,  Yoshiyuki Fujino ,  Masayuki Iketani

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/78 ,  G11C11/417 ,  G11C11/419 ,  G11C7/14 ,  G11C7/22

摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

摘要翻译： 延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。 全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。 响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。 写入门响应于列选择信号将位线连接到本地写数据总线。 延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。 提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。