Invention Grant
- Patent Title: Digital memory circuit having a plurality of segmented memory areas
- Patent Title (中): 数字存储电路具有多个分段存储区
-
Application No.: US10266190Application Date: 2002-10-07
-
Publication No.: US06711085B2Publication Date: 2004-03-23
- Inventor: Helmut Fischer , Johann Pfeiffer
- Applicant: Helmut Fischer , Johann Pfeiffer
- Priority: DE10149098 20011005
- Main IPC: G11C800
- IPC: G11C800

Abstract:
A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is subdivided into a plurality of adjacent groups which each form a segment. For each segment, provision is made of a separate set of two-conductor local data lines which lead via line switches to two-conductor master data lines common to all the memory areas. Furthermore, precharge devices are provided in order to equalize the potentials of the conductors of the local data lines and the conductors of the master data lines, the equalization potential for the local data lines being different than the equalization potential for the master data lines. A line switch control device provides for closing only of the line switches on those local data lines which belong to the segment in which a write or read mode takes place.
Public/Granted literature
- US20030067820A1 Digital memory circuit having a plurality of segmented memory areas Public/Granted day:2003-04-10
Information query