发明授权
US06711085B2 Digital memory circuit having a plurality of segmented memory areas 有权
数字存储电路具有多个分段存储区

  • 专利标题: Digital memory circuit having a plurality of segmented memory areas
  • 专利标题(中): 数字存储电路具有多个分段存储区
  • 申请号: US10266190
    申请日: 2002-10-07
  • 公开(公告)号: US06711085B2
    公开(公告)日: 2004-03-23
  • 发明人: Helmut FischerJohann Pfeiffer
  • 申请人: Helmut FischerJohann Pfeiffer
  • 优先权: DE10149098 20011005
  • 主分类号: G11C800
  • IPC分类号: G11C800
Digital memory circuit having a plurality of segmented memory areas
摘要:
A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is subdivided into a plurality of adjacent groups which each form a segment. For each segment, provision is made of a separate set of two-conductor local data lines which lead via line switches to two-conductor master data lines common to all the memory areas. Furthermore, precharge devices are provided in order to equalize the potentials of the conductors of the local data lines and the conductors of the master data lines, the equalization potential for the local data lines being different than the equalization potential for the master data lines. A line switch control device provides for closing only of the line switches on those local data lines which belong to the segment in which a write or read mode takes place.
信息查询
0/0