An integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry is provided. The ESD protection circuit is coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The core protection circuit and the sensitive core circuit are coupled in series between the VDD and VSS voltage supply terminals, with the core protection circuit coupled to the VDD voltage supply terminal. The sensitive core circuit has a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit. The core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. The core protection circuit is further configured to disconnect the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds the nominal VDD supply voltage by a predetermined amount.