公开(公告)号：US06421265B1

公开(公告)日：2002-07-16

申请号：US09816742

申请日：2001-03-22

申请人： Chuen-Der Lien ,  Chau-Chin Wu ,  Ta-Ke Tien

发明人： Chuen-Der Lien ,  Chau-Chin Wu ,  Ta-Ke Tien

IPC分类号： G11C1500

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A CAM cell including three-transistor (3T) or four-transistor (4T) DRAM cells. Data is stored using intrinsic capacitance of each 3T or 4T DRAM cell, and is applied to the gate terminal of a pull-down transistor. Read operations are performed in the 3T and 4T DRAM cells without disturbing the stored data value by applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of a pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells.

摘要翻译： 包括三晶体管（3T）或四晶体管（4T）DRAM单元的CAM单元。 使用每个3T或4T DRAM单元的固有电容来存储数据，并且被施加到下拉晶体管的栅极端子。 通过将存储的数据值应用于下拉晶体管的栅极端子并检测拉动的操作状态（即，导通或关闭），在3T和4T DRAM单元中执行读操作，而不会干扰存储的数据值 降低晶体管，从而避免与1T DRAM单元相关的电荷共享问题。

公开(公告)号：US06724601B2

公开(公告)日：2004-04-20

申请号：US09811114

申请日：2001-03-16

申请人： Chuen-Der Lien ,  Chau-Chin Wu ,  Ta-Ke Tien

发明人： Chuen-Der Lien ,  Chau-Chin Wu ,  Ta-Ke Tien

IPC分类号： H02H900

CPC分类号： H01L27/0251

摘要： An integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry is provided. The ESD protection circuit is coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The core protection circuit and the sensitive core circuit are coupled in series between the VDD and VSS voltage supply terminals, with the core protection circuit coupled to the VDD voltage supply terminal. The sensitive core circuit has a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit. The core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. The core protection circuit is further configured to disconnect the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds the nominal VDD supply voltage by a predetermined amount.

摘要翻译： 提供具有静电放电（ESD）保护电路，核心保护电路，敏感核心电路和外围电路的集成电路。 ESD保护电路耦合在VDD电压端子和VSS电压端子之间，能够为外围电路提供保护。 ESD保护电路需要核心保护电路的帮助来保护敏感的核心电路。 核心保护电路和敏感核心电路串联在VDD和VSS电压端子之间，核心保护电路耦合到VDD电源端。 敏感核心电路具有VCC电压供应端，耦合以从核心保护电路接收VCC电源电压。 核心保护电路被配置为使得在电源上的VCC电源电压相对于VDD电压端上升的电压缓慢上升。 核心保护电路还被配置为当VDD电压端子上的电压超过标称VDD电源电压预定量时，将VCC电压源端子与VDD电压源断开。

公开(公告)号：US07474011B2

公开(公告)日：2009-01-06

申请号：US11527374

申请日：2006-09-25

申请人： Chuen-Der Lien ,  Ta-Ke Tien ,  Pao-Lu Louis Huang

发明人： Chuen-Der Lien ,  Ta-Ke Tien ,  Pao-Lu Louis Huang

IPC分类号： H01L27/00 ,  G06F17/50

CPC分类号： G01R31/2853 ,  G06F17/5036 ,  Y10S257/929

摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.

摘要翻译： 一种用于估计集成电路中单事件闩锁发生的过程和系统。 该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。 发现在不规则形状的井中的每个连接也被识别。 最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

公开(公告)号：US20080122473A1

公开(公告)日：2008-05-29

申请号：US11527374

申请日：2006-09-25

申请人： Chuen-Der Lien ,  Ta-Ke Tien ,  Pao-Lu Louis Huang

发明人： Chuen-Der Lien ,  Ta-Ke Tien ,  Pao-Lu Louis Huang

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G01R31/2853 ,  G06F17/5036 ,  Y10S257/929

摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.

摘要翻译： 一种用于估计集成电路中单事件闩锁发生的过程和系统。 该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。 发现在不规则形状的井中的每个连接也被识别。 最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

公开(公告)号：US06307399B1

公开(公告)日：2001-10-23

申请号：US09089309

申请日：1998-06-02

申请人： Chuen-Der Lien ,  Ta-Ke Tien

发明人： Chuen-Der Lien ,  Ta-Ke Tien

IPC分类号： H03K190175

CPC分类号： H03K19/00361 ,  H03K17/167

摘要： In a buffer circuit a pull-up circuit causes an output terminal of the buffer circuit make a transition from a low voltage to a high, and a feedback circuit increases the rate of the transition during the part of the transition when the output terminal moves from the low voltage to a predesignated voltage, the predesignated voltage being a value between but different from the low and high voltages. In another buffer circuit powered by a power supply voltage, a pull-up transistor causes a signal at an output terminal of the buffer circuit make a transition from a low voltage to a high voltage, and a converter circuit converts the power supply voltage to a lower voltage, the lower voltage powering the pull-up transistor.

摘要翻译： 在缓冲电路中，上拉电路使得缓冲电路的输出端子从低电压转变到高电平，并且反馈电路在输出端子从...移动时增加转换部分期间的转换速率 低电压到预定电压，预定电压是一个但不同于低电压和高电压之间的值。 在由电源电压供电的另一个缓冲电路中，上拉晶体管使得缓冲电路的输出端的信号从低电压转变为高电压，并且转换器电路将电源电压转换为 较低的电压，较低的电压供电上拉晶体管。

公开(公告)号：US07706113B1

公开(公告)日：2010-04-27

申请号：US11668360

申请日：2007-01-29

申请人： Chuen-Der Lien ,  Ta-Ke Tien

发明人： Chuen-Der Lien ,  Ta-Ke Tien

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H01L27/0285

摘要： A system and method are provided for electrostatic discharge (ESD) protection circuit having overshoot and undershoot voltage protection during a power supply ramp-up of the circuit. In a specific embodiment, the ESD protection circuit of the present invention includes an ESD discharge circuit coupled between a power supply node and a ground supply node, a trigger circuit coupled to the ESD discharge circuit, the trigger circuit to turn the ESD discharge circuit on in the presence of a voltage spike during the power supply ramp-up and to turn the ESD discharge circuit off in the absence of a voltage spike during the power supply ramp-up, and a delay circuit coupled between the discharge circuit and the trigger circuit, the delay circuit to slow down the turn-off of the discharge circuit to prevent an overshoot or undershoot voltage condition during the power supply ramp-up of the circuit.

摘要翻译： 提供一种用于在电路的电源斜升期间具有过冲和下冲电压保护的静电放电（ESD）保护电路的系统和方法。 在具体实施例中，本发明的ESD保护电路包括耦合在电源节点和接地电源节点之间的ESD放电电路，耦合到ESD放电电路的触发电路，触发电路以使ESD放电电路转向 在电源斜坡上升期间存在电压尖峰，并且在电源上升期间没有电压尖峰时将ESD放电电路断开，以及耦合在放电电路和触发电路之间的延迟电路 延迟电路，以减缓放电电路的关断，以防止在电路的电源上升期间的过冲或下冲电压状况。

公开(公告)号：US07102862B1

公开(公告)日：2006-09-05

申请号：US10283532

申请日：2002-10-29

申请人： Chuen-Der Lien ,  Ta-Ke Tien

发明人： Chuen-Der Lien ,  Ta-Ke Tien

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： Circuits are disclosed for protecting internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge (EDS). One example circuit includes a trigger circuit including a transistor and a capacitor arranged in series between DC pads. The trigger circuit generates a trigger signal to a discharge circuit connected between the DC pads to shunt charge from one of the DC pads to the other. The RC delay associated with the transistor and capacitor of the trigger circuit may be designed such that the trigger circuit generates the trigger signal in response to an ESD event, but not in response to high positive spikes on one of the DC pads during normal operation.

摘要翻译： 公开了用于保护半导体芯片的内部电路免受由静电放电（EDS）引起的电源电压的电路。 一个示例电路包括触发电路，其包括串联布置在DC焊盘之间的晶体管和电容器。 触发电路产生触发信号到连接在DC焊盘之间的放电电路，以将电荷从DC焊盘之一分流到另一个。 可以设计与触发电路的晶体管和电容器相关联的RC延迟，使得触发电路响应于ESD事件而产生触发信号，但不响应于在正常操作期间的一个DC焊盘上的高正尖峰。

公开(公告)号：US06204557B1

公开(公告)日：2001-03-20

申请号：US09394667

申请日：1999-09-13

申请人： Chuen-Der Lien ,  Chun-Ya Chen ,  Pauli Hsueh ,  Ta-Ke Tien ,  Leonard Perham

发明人： Chuen-Der Lien ,  Chun-Ya Chen ,  Pauli Hsueh ,  Ta-Ke Tien ,  Leonard Perham

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure that includes a patterned uppermost conductive layer having a current-carrying trace. The current-carrying trace is connected to an underlying substrate by a multi-layer interconnect structure. The current-carrying trace, which is located around the outer edges of the integrated circuit structure, has at least one edge exhibiting a serpentine pattern. A topside film is located over the patterned uppermost conductive layer, wherein the topside film exhibits an increased thickness adjacent to the serpentine pattern. The increased thickness of the serpentine pattern results in a relatively strong topside film structure near the edges of the substrate. As a result, the portions of the topside film located over inner traces of the uppermost conductive layer are protected from excessive forces during thermal cycling.

摘要翻译： 一种集成电路结构，其包括具有载流迹线的图案化最上层的导电层。 载流迹线通过多层互连结构连接到下层衬底。 位于集成电路结构的外边缘周围的载流迹线具有至少一个呈现蛇形图案的边缘。 顶层膜位于图案化的最上层导电层上方，其中顶侧膜表现出与蛇形图案相邻的增加的厚度。 蛇纹石图案的增加的厚度导致靠近基底边缘的相对强的顶侧膜结构。 结果，在热循环期间，保护位于最上面的导电层的内部迹线上方的顶侧膜的部分免受过多的力。

公开(公告)号：US07545660B1

公开(公告)日：2009-06-09

申请号：US11931868

申请日：2007-10-31

申请人： Chuen-Der Lien ,  Chau-Chin Wu

发明人： Chuen-Der Lien ,  Chau-Chin Wu

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/02

摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

摘要翻译： 已经公开了一种具有减小的交叉耦合干扰的CAM的方法和装置。

公开(公告)号：US06781857B1

公开(公告)日：2004-08-24

申请号：US10306799

申请日：2002-11-27

申请人： Chuen-Der Lien ,  Chau-Chin Wu ,  Mark Baumann

发明人： Chuen-Der Lien ,  Chau-Chin Wu ,  Mark Baumann

IPC分类号： G11C1500

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A CAM device includes an array of multi-compare port CAM cells therein. The CAM cells are configured to support concurrent search operations between multiple distinct search words and entries within the rows of the CAM array. These concurrent search operations may be performed in-sync with respective clock signals that are asynchronous relative to each other.

摘要翻译： CAM设备包括其中的多比较端口CAM单元阵列。 CAM单元被配置为支持多个不同搜索词和CAM阵列的行内的条目之间的并发搜索操作。 这些并发搜索操作可以与相对于彼此异步的各个时钟信号同步执行。