发明授权
US06724686B2 Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
失效
可操作的同步半导体存储器件在单数据速率模式和双数据速率模式之间切换
- 专利标题： Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode
- 专利标题（中）： 可操作的同步半导体存储器件在单数据速率模式和双数据速率模式之间切换
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申请号： US10339288申请日： 2003-01-10
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公开(公告)号： US06724686B2公开(公告)日： 2004-04-20
- 发明人: Tsukasa Ooishi , Masatoshi Ishikawa
- 申请人： Tsukasa Ooishi , Masatoshi Ishikawa
- 优先权： JP10-162477 19980610; JP10-292561 19981014
- 主分类号： G11C800
- IPC分类号： G11C800
摘要：
A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.
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