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    Thin film magnetic memory device sharing an access element by a plurality of memory cells
    2.
    发明授权
    Thin film magnetic memory device sharing an access element by a plurality of memory cells 失效
    薄膜磁存储器件通过多个存储单元共享存取元件

    公开(公告)号：US06757191B2

    公开(公告)日：2004-06-29

    申请号：US10222793

    申请日：2002-08-19

    申请人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

    发明人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

    IPC分类号： G11C1114

    CPC分类号： G11C11/16

    摘要： A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

    摘要翻译： 每个MTJ（磁性隧道结）存储单元的隧道磁阻元件连接在位线和带之间。 每个带由多个相同子阵列中的行方向上彼此相邻的隧道磁阻元件共享。 每个存取晶体管连接在对应的带和接地电压之间，并响应于相应的字线而导通/截止。 由于可以对每个隧道磁阻元件不具有存取晶体管的结构进行数据读取操作，因此可以减小阵列面积。

    Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation
    3.
    发明授权
    Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation 有权

    公开(公告)号：US06292015B1

    公开(公告)日：2001-09-18

    申请号：US09272316

    申请日：1999-03-19

    申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    IPC分类号： H03K1716

    CPC分类号： G11C5/147 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

    Semiconductor memory device preventing erroneous writing in write operation and delay in read operation
    5.
    发明授权
    Semiconductor memory device preventing erroneous writing in write operation and delay in read operation 有权
    半导体存储器件防止写操作中的错误写入和读操作延迟

    公开(公告)号：US06584005B1

    公开(公告)日：2003-06-24

    申请号：US10302963

    申请日：2002-11-25

    申请人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

    发明人： Hiroshi Kato ,  Masatoshi Ishikawa ,  Tsukasa Ooishi ,  Jun Ohtani ,  Hideto Hidaka

    IPC分类号： G11C506

    CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08

    摘要： In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

    摘要翻译： 在写入操作和读取操作中，基于存储器阵列中的所选存储单元列，将多个位线分成第一位线组和第二位线组。 第一位线组连接到第一和第二电压中的一个，并且第二位线组连接到另一个电压。 因此，当对应于所选择的存储单元的字线被激活时，所选存储单元行中未选择的存储单元的源极和漏极被设置为相同的电压电平。 因此，响应于字线的激活，不产生由每个位线的充电和放电产生的充电/放电电流。 这防止了对未选择的存储单元的错误写入和由于产生充电/放电电流引起的读取操作的延迟。

    Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation
    7.
    发明授权
    Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation 失效
    包括逻辑门的半导体集成电路器件，其降低功耗和高速操作

    公开(公告)号：US06794904B2

    公开(公告)日：2004-09-21

    申请号：US10281951

    申请日：2002-10-29

    申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    IPC分类号： H01L2500

    CPC分类号： G11C5/147 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

    摘要翻译： 半导体集成电路器件具有用于逻辑电路的分层供电系统。 逆变器具有来自主电源线和较高电位的副电源线以及较低电位的主地线和次地线的电源。 放置内部电源降压转换器以将主电源线的电压设置为高于较高电位的正常工作电压。 放置内部电源升压电路，将主接地线的电压设定为低于较低电位的正常工作电压。 当各个电源线由开关晶体管短路时，每个电源线的电压可以保持在操作电源电压。

    Thin film magnetic memory device having an access element shared by a plurality of memory cells
    8.
    发明授权
    Thin film magnetic memory device having an access element shared by a plurality of memory cells 失效
    具有由多个存储单元共享的访问单元的薄膜磁存储器件

    公开(公告)号：US06788571B2

    公开(公告)日：2004-09-07

    申请号：US10301838

    申请日：2002-11-22

    申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    IPC分类号： G11C1114

    CPC分类号： G11C11/16

    摘要： A tunneling magneto-resistance element forming an MTJ memory cell is connected between a bit line and a strap. In each memory cell column, the strap is shared by the plurality of tunneling magneto-resistance elements in the same row block. The access transistor is connected between strap and ground voltage, and is turned on/off in response to a corresponding word line. Storage data is read from the selected memory cell based on a comparison between results of data reading effected on a memory cell group coupled to the same strap before and after application of a predetermined magnetic field to the selected memory cell.

    摘要翻译： 形成MTJ存储单元的隧道磁阻元件连接在位线和带之间。 在每个存储单元列中，带由同一行块中的多个隧道磁阻元件共享。 存取晶体管连接在带和接地电压之间，并响应于相应的字线而导通/截止。 基于在将预定磁场施加到所选择的存储器单元之前和之后，在耦合到相同带的存储器单元组上进行的数据读取的结果之间的比较，从所选择的存储器单元中读取存储数据。

    Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation
    9.
    发明授权
    Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation 有权
    包括逻辑门的半导体集成电路器件，其降低功耗和高速操作

    公开(公告)号：US06483165B2

    公开(公告)日：2002-11-19

    申请号：US09816406

    申请日：2001-03-26

    申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

    IPC分类号： H01L2900

    CPC分类号： G11C5/147 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

    摘要翻译： 半导体集成电路器件具有用于逻辑电路的分层供电系统。 逆变器具有来自主电源线和较高电位的副电源线以及较低电位的主地线和次地线的电源。 放置内部电源降压转换器以将主电源线的电压设置为高于较高电位的正常工作电压。 放置内部电源升压电路，将主接地线的电压设定为低于较低电位的正常工作电压。 当各个电源线由开关晶体管短路时，每个电源线的电压可以保持在操作电源电压。