发明授权
US06728890B1 Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component
有权
响应于来自请求组件的信号来控制总线时钟频率的方法和装置
- 专利标题： Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component
- 专利标题（中）： 响应于来自请求组件的信号来控制总线时钟频率的方法和装置
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申请号： US09670417申请日： 2000-09-26
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公开(公告)号： US06728890B1公开(公告)日： 2004-04-27
- 发明人: Russell N. Mirov , Michel Cekleov , Mark Young , William M. Baldwin
- 申请人： Russell N. Mirov , Michel Cekleov , Mark Young , William M. Baldwin
- 主分类号： G06R126
- IPC分类号： G06R126
摘要：
A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.
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