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1.发明授权Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component 有权响应于来自请求组件的信号来控制总线时钟频率的方法和装置公开(公告)号：US06728890B1
公开(公告)日：2004-04-27
申请号：US09670417
申请日：2000-09-26
IPC分类号： G06R126
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126
摘要： A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.
摘要翻译： 提供一种用于控制总线和与其耦合的部件的操作的方法。 该方法包括从耦合到总线的组件中的一个接收对总线事务的请求。 此后，提供给至少请求组件的时钟信号的频率增加，并且对所请求的总线事务进行维修。 在请求的总线事务完成时，提供给至少请求组件的时钟信号的频率降低。
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公开(公告)号：US06691215B1
公开(公告)日：2004-02-10
申请号：US09670418
申请日：2000-09-26
IPC分类号： G06F1200
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.
摘要翻译： 提供了一种存储系统。 存储器系统包括存储器，时钟信号发生器，锁相环电路和旁路电路。 时钟信号发生器产生第一时钟信号。 时钟信号发生器具有第一工作模式，其中第一时钟信号具有第一频率和第二工作模式，其中第一时钟信号具有第二频率。 锁相环电路与存储器相关联，并且适于接收第一时钟信号并向存储器提供同步的第二时钟信号。 旁路电路适于在第二操作模式中将第一时钟信号传送到存储器。
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公开(公告)号：US06718473B1
公开(公告)日：2004-04-06
申请号：US09670420
申请日：2000-09-26
IPC分类号： G06R132
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.
摘要翻译： 在本发明的一个方面，提供了一种用于控制锁相环电路的操作的方法。 该方法包括监视系统时钟的频率，并且响应于系统时钟的检测频率大于预选设定点而递送第一信号。 响应于系统时钟的检测频率小于预先选定的设定点而递送第二信号。 响应于接收到第一信号来选择锁相环电路的第一操作模式。 第一种操作模式允许锁相环电路与第一预选频率范围内的时钟信号同步。 响应于接收到第二信号来选择锁相环电路的第二操作模式。 第二种操作模式允许锁相环电路与第二预选频率范围内的时钟信号同步。
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4.发明授权Method and apparatus for providing total and partial store ordering for a memory in multi-processor system 失效用于在多处理器系统中为存储器提供全部和部分存储顺序的方法和装置
公开(公告)号：US5265233A
公开(公告)日：1993-11-23
申请号：US702781
申请日：1991-05-17
CPC分类号： G06F9/3004 , G06F12/0833 , G06F9/30054 , G06F9/30079 , G06F9/30087 , G06F9/3834
摘要： An improved memory model and implementation is disclosed. The memory model includes a Total Store Ordering (TSO) and Partial Store Ordering (PSO) memory model to provide a partial order for the memory operations which are issued by multiple processors. The TSO memory model includes a FIFO Store Buffer for Store, and Atomic Load-Store operations. The Load operations are not placed in the FIFO Store Buffer. The Load operation checks for a value stored in the same location in the FIFO Store Buffer; if no such value is found, then requested value is returned from memory. The PSO model also includes a Store Buffer for Store, and Atomic Load-Store operations. However, unlike the TSO model, the Store Buffer in the PSO model is not FIFO. The processors in the PSO model may issue the Store and Atomic Load-Store in a certain order; however, such operations may be executed by memory out of the order issued by the processors. The execution order is assured only by address matching and the STBAR operation. Two Store operations separated by a STBAR operations guarantees memory will execute the operations in an order issued by the processors. Load operations in the PSO model are not placed in the Store Buffer. The Load operation first checks for a value stored in the same location in the Store Buffer; if no such value is found, then the requested value is returned from memory.
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公开(公告)号：US06700421B1
公开(公告)日：2004-03-02
申请号：US09669825
申请日：2000-09-26
IPC分类号： H03L706
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal. The clock tree is coupled to receive the third clock signal and deliver at least one fourth clock signal. The feedback path is coupled to deliver the fourth clock signal to the second input terminal of the phase comparator.
摘要翻译： 提供了一个锁相环电路。 锁相环电路由第一和第二除N计数器，相位比较器，压控振荡器，时钟树和反馈路径组成。 第一分频计数器适于接收第一时钟信号并提供第二时钟信号。 相位比较器具有第一和第二输入端子和输出端子。 相位比较器适于比较施加到第一和第二输入端的信号的相位，并在输出端递送具有表示信号相位差的幅度的信号。 第一输入端耦合以接收第二时钟信号。 电压控制振荡器被耦合以接收相位差信号并传送具有对其响应的频率的第三时钟信号。 第二分频计数器被耦合以接收第三时钟信号并传送第四时钟信号。 时钟树被耦合以接收第三时钟信号并且递送至少一个第四时钟信号。 反馈路径被耦合以将第四时钟信号传送到相位比较器的第二输入端。
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公开(公告)号：US06608476B1
公开(公告)日：2003-08-19
申请号：US09670143
申请日：2000-09-26
IPC分类号： G01R1132
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.
摘要翻译： 提供一种用于通过监视电子设备的操作特性来操作电子设备的方法，以及根据所监视的操作特性来确定在第一，第二或第三操作模式下操作电子设备内的部件的至少一部分。 第一，第二和第三种操作模式以第一，第二和第三种不同的速率消耗功率。 指示部件的至少一部分在第一，第二和第三模式之间切换。
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7.发明授权Method and apparatus for controlling transitions between a first and a second clock frequency 有权用于控制第一和第二时钟频率之间的转换的方法和装置公开(公告)号：US06845457B1
公开(公告)日：2005-01-18
申请号：US09670419
申请日：2000-09-26
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126
摘要： A method is provided for controlling transitions between a first and second clock frequency signal in first and second components electrically coupled together and in communication with one another. The method comprises asserting a freeze signal to cause communications between the first and second components to cease. A freeze acknowledge signal is then received from the first and second components, indicating that communications therebetween have ceased. A change signal is delivered to the first and second components to cause the components to switch between the first and second clock frequency signals.
摘要翻译： 提供了一种用于控制第一和第二组件中的第一和第二时钟频率信号之间的转换的方法，所述第一和第二组件电耦合在一起并且彼此通信。 该方法包括断言冻结信号以使第一和第二组件之间的通信停止。 然后从第一和第二组件接收到冻结确认信号，表明它们之间的通信已经停止。 改变信号被传送到第一和第二分量，以使得分量在第一和第二时钟频率信号之间切换。
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8.发明授权Method and apparatus for invalidating a cache line without data return in a multi-node architecture 有权在多节点体系结构中无数据返回使高速缓存行无效的方法和装置公开(公告)号：US06772298B2
公开(公告)日：2004-08-03
申请号：US09739667
申请日：2000-12-20
申请人： Manoj Khare , Akhilesh Kumar , Ken Creta , Lily P. Looi , Robert T. George , Michel Cekleov
发明人： Manoj Khare , Akhilesh Kumar , Ken Creta , Lily P. Looi , Robert T. George , Michel Cekleov
IPC分类号： G06F1200
CPC分类号： G06F12/0808 , G06F12/0817
摘要： A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another node without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.
摘要翻译： 一种使具有包括处理器和高速缓冲存储器的多个节点的系统中的高速缓存行无效的方法。 从第一个节点发送请求使缓存特定内存块的缓存行无效。 请求是使另一个节点中的高速缓存行无效的请求，而不将第一个节点的数据存储在高速缓存行中将被无效。 在一个实施例中，即使高速缓存行处于修改状态，也将无效的高速缓存行中的数据返回到第一节点。 在另一实施例中，将新数据写入缓存特定存储器块的第一节点中的高速缓存行，而不将存储在该高速缓存行中的旧数据写回存储器。
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9.发明授权Apparatus for maintaining consistency in a multiprocessor computer system using virtual caching 失效用于使用虚拟缓存来维持多处理器计算机系统中的一致性的装置
公开(公告)号：US5361340A
公开(公告)日：1994-11-01
申请号：US28766
申请日：1993-03-09
申请人： Edmund Kelly , Michel Cekleov , Michel Dubois
发明人： Edmund Kelly , Michel Cekleov , Michel Dubois
CPC分类号： G06F12/0831 , G06F12/1063
摘要： A computer system includes first and second processors each having a virtual cache memory, a main memory, a bus coupled to the main memory and the processors, and apparatus for addressing the cache associated with each processor for providing that the data in each virtual cache stores data from the same physical location in main memory at a same index position in each virtual cache, a memory management unit (MMU) coupled to each processor such that addressing information is transferred to each memory management unit to indicate the virtual address of data to be written to the virtual cache, the memory management unit generating from the virtual address a physical address, and determining whether any other virtual cache includes data from the same physical memory positions.
摘要翻译： 计算机系统包括第一和第二处理器，每个具有虚拟高速缓冲存储器，主存储器，耦合到主存储器和处理器的总线，以及用于寻址与每个处理器相关联的高速缓存的装置，用于提供每个虚拟高速缓存中的数据存储 来自每个虚拟高速缓存中相同索引位置的主存储器中相同物理位置的数据，耦合到每个处理器的存储器管理单元（MMU），使得寻址信息被传送到每个存储器管理单元以指示数据的虚拟地址 写入所述虚拟高速缓存，所述存储器管理单元从所述虚拟地址生成物理地址，以及确定任何其他虚拟高速缓存是否包括来自相同物理存储器位置的数据。
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10.发明授权Method and apparatus for reducing power consumption in a cache memory system 有权用于降低高速缓冲存储器系统中的功率消耗的方法和装置公开(公告)号：US06836824B1
公开(公告)日：2004-12-28
申请号：US09670368
申请日：2000-09-26
IPC分类号： G06F1200
CPC分类号： G06F1/08 , G06F1/206 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/16
摘要： A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.
摘要翻译： 提供了一种用于操作具有休眠模式的高速缓存的方法。 高速缓存位于计算机系统的存储器层次结构中，并且该方法包括接收第一高速缓存请求并且服务于第一高速缓存请求。 响应于完成第一高速缓存请求的服务而断言睡眠模式信号。 此后，接收到第二高速缓存请求，并且响应于接收到第二高速缓存请求，休眠模式信号被断言。 此后，服务第二高速缓存请求。
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