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1.发明授权Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component 有权响应于来自请求组件的信号来控制总线时钟频率的方法和装置公开(公告)号：US06728890B1
公开(公告)日：2004-04-27
申请号：US09670417
申请日：2000-09-26
IPC分类号： G06R126
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126
摘要： A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.
摘要翻译： 提供一种用于控制总线和与其耦合的部件的操作的方法。 该方法包括从耦合到总线的组件中的一个接收对总线事务的请求。 此后，提供给至少请求组件的时钟信号的频率增加，并且对所请求的总线事务进行维修。 在请求的总线事务完成时，提供给至少请求组件的时钟信号的频率降低。
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公开(公告)号：US06691215B1
公开(公告)日：2004-02-10
申请号：US09670418
申请日：2000-09-26
IPC分类号： G06F1200
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.
摘要翻译： 提供了一种存储系统。 存储器系统包括存储器，时钟信号发生器，锁相环电路和旁路电路。 时钟信号发生器产生第一时钟信号。 时钟信号发生器具有第一工作模式，其中第一时钟信号具有第一频率和第二工作模式，其中第一时钟信号具有第二频率。 锁相环电路与存储器相关联，并且适于接收第一时钟信号并向存储器提供同步的第二时钟信号。 旁路电路适于在第二操作模式中将第一时钟信号传送到存储器。
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公开(公告)号：US06700421B1
公开(公告)日：2004-03-02
申请号：US09669825
申请日：2000-09-26
IPC分类号： H03L706
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal. The clock tree is coupled to receive the third clock signal and deliver at least one fourth clock signal. The feedback path is coupled to deliver the fourth clock signal to the second input terminal of the phase comparator.
摘要翻译： 提供了一个锁相环电路。 锁相环电路由第一和第二除N计数器，相位比较器，压控振荡器，时钟树和反馈路径组成。 第一分频计数器适于接收第一时钟信号并提供第二时钟信号。 相位比较器具有第一和第二输入端子和输出端子。 相位比较器适于比较施加到第一和第二输入端的信号的相位，并在输出端递送具有表示信号相位差的幅度的信号。 第一输入端耦合以接收第二时钟信号。 电压控制振荡器被耦合以接收相位差信号并传送具有对其响应的频率的第三时钟信号。 第二分频计数器被耦合以接收第三时钟信号并传送第四时钟信号。 时钟树被耦合以接收第三时钟信号并且递送至少一个第四时钟信号。 反馈路径被耦合以将第四时钟信号传送到相位比较器的第二输入端。
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公开(公告)号：US06608476B1
公开(公告)日：2003-08-19
申请号：US09670143
申请日：2000-09-26
IPC分类号： G01R1132
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.
摘要翻译： 提供一种用于通过监视电子设备的操作特性来操作电子设备的方法，以及根据所监视的操作特性来确定在第一，第二或第三操作模式下操作电子设备内的部件的至少一部分。 第一，第二和第三种操作模式以第一，第二和第三种不同的速率消耗功率。 指示部件的至少一部分在第一，第二和第三模式之间切换。
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5.发明授权Method and apparatus for controlling transitions between a first and a second clock frequency 有权用于控制第一和第二时钟频率之间的转换的方法和装置公开(公告)号：US06845457B1
公开(公告)日：2005-01-18
申请号：US09670419
申请日：2000-09-26
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126
摘要： A method is provided for controlling transitions between a first and second clock frequency signal in first and second components electrically coupled together and in communication with one another. The method comprises asserting a freeze signal to cause communications between the first and second components to cease. A freeze acknowledge signal is then received from the first and second components, indicating that communications therebetween have ceased. A change signal is delivered to the first and second components to cause the components to switch between the first and second clock frequency signals.
摘要翻译： 提供了一种用于控制第一和第二组件中的第一和第二时钟频率信号之间的转换的方法，所述第一和第二组件电耦合在一起并且彼此通信。 该方法包括断言冻结信号以使第一和第二组件之间的通信停止。 然后从第一和第二组件接收到冻结确认信号，表明它们之间的通信已经停止。 改变信号被传送到第一和第二分量，以使得分量在第一和第二时钟频率信号之间切换。
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6.发明授权Method and apparatus for reducing power consumption in a cache memory system 有权用于降低高速缓冲存储器系统中的功率消耗的方法和装置公开(公告)号：US06836824B1
公开(公告)日：2004-12-28
申请号：US09670368
申请日：2000-09-26
IPC分类号： G06F1200
CPC分类号： G06F1/08 , G06F1/206 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/16
摘要： A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.
摘要翻译： 提供了一种用于操作具有休眠模式的高速缓存的方法。 高速缓存位于计算机系统的存储器层次结构中，并且该方法包括接收第一高速缓存请求并且服务于第一高速缓存请求。 响应于完成第一高速缓存请求的服务而断言睡眠模式信号。 此后，接收到第二高速缓存请求，并且响应于接收到第二高速缓存请求，休眠模式信号被断言。 此后，服务第二高速缓存请求。
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公开(公告)号：US06748546B1
公开(公告)日：2004-06-08
申请号：US09670041
申请日：2000-09-26
IPC分类号： G06F126
CPC分类号： G06F1/206 , G06F1/08 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/16
摘要： A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.
摘要翻译： 提供了一种用于控制计算机系统中的热循环的方法。 该方法包括接收将计算机系统从第一操作模式转换到第二操作模式的请求，其中在第二操作模式中消耗较少的功率。 确定计算机系统在第一和第二操作模式之间转换的历史速率，并且响应于历史速率小于第一预选设定值而允许所请求的转换，但是响应于历史速率更大而拒绝 比第一个预选设定值。
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公开(公告)号：US06528974B1
公开(公告)日：2003-03-04
申请号：US09669357
申请日：2000-09-26
IPC分类号： G05F1577
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.
摘要翻译： 提供电源。 电源由第一电源模块，第二电源模块和控制器组成。 第一电源模块能够提供第一预选量的电力。 第二电源模块能够传递第二预选量的电力。 第一和第二功率模块耦合在一起，以能够传递与第一和第二预选量的功率有关的总量的功率。 控制器适于选择性地使得第一和第二功率模块能够以第一预选量，第二预选量和总量中的一种来供电。
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公开(公告)号：US06718473B1
公开(公告)日：2004-04-06
申请号：US09670420
申请日：2000-09-26
IPC分类号： G06R132
CPC分类号： G06F1/324 , G06F1/08 , G06F1/206 , G06F1/3203 , Y02D10/126 , Y02D10/16
摘要： In one aspect of the present invention, a method for controlling the operation of a phase locked loop circuit is provided. The method is comprised of monitoring a frequency of a system clock, and a first signal is delivered in response to the detected frequency of the system clock being greater than a preselected setpoint. A second signal is delivered in response to the detected frequency of the system clock being less than a preselected setpoint. A first operating mode of the phase locked loop circuit is selected in response to receiving the first signal. The first mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a first preselected range of frequencies. A second operating mode of the phase locked loop circuit is selected in response to receiving the second signal. The second mode of operation allows the phase locked loop circuit to synchronize with a clock signal in a second preselected range of frequencies.
摘要翻译： 在本发明的一个方面，提供了一种用于控制锁相环电路的操作的方法。 该方法包括监视系统时钟的频率，并且响应于系统时钟的检测频率大于预选设定点而递送第一信号。 响应于系统时钟的检测频率小于预先选定的设定点而递送第二信号。 响应于接收到第一信号来选择锁相环电路的第一操作模式。 第一种操作模式允许锁相环电路与第一预选频率范围内的时钟信号同步。 响应于接收到第二信号来选择锁相环电路的第二操作模式。 第二种操作模式允许锁相环电路与第二预选频率范围内的时钟信号同步。
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公开(公告)号：US06880970B2
公开(公告)日：2005-04-19
申请号：US10453752
申请日：2003-06-03
申请人： Russell N. Mirov
发明人： Russell N. Mirov
CPC分类号： H05K1/0201 , G01K1/20 , H05K2201/062 , H05K2201/09063 , H05K2201/10151
摘要： A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed circuit board is provided. Generally, a thermal isolation region, which may be comprised of a plurality of openings in the printed circuit board, is disposed about the temperature sensor to interrupt conductive transfer of heat from the heat generating component to the temperature sensor. The openings extend sufficiently far into the printed circuit board to remove at least a portion of a conductive layer, such as a power plane from the region surrounding the temperature sensor. Electrical power and signals may be provided to the temperature sensor through regions intermediate the openings.
摘要翻译： 提供了一种用于将安装在印刷电路板上的温度传感器与安装在印刷电路板上的发热部件进行热隔离的方法和装置。 通常，可以在印刷电路板中由多个开口组成的热隔离区域设置在温度传感器周围，以中断热量从发热部件到温度传感器的传导传递。 这些开口足够远地延伸到印刷电路板中以从包围温度传感器的区域移除至少一部分导电层，例如电源平面。 可以通过开口之间的区域向温度传感器提供电力和信号。
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