发明授权
US06735688B1 Processor having replay architecture with fast and slow replay paths
有权
具有重放架构的处理器具有快速和慢速的重放路径
- 专利标题： Processor having replay architecture with fast and slow replay paths
- 专利标题（中）： 具有重放架构的处理器具有快速和慢速的重放路径
-
申请号： US09503853申请日： 2000-02-14
-
公开(公告)号： US06735688B1公开(公告)日： 2004-05-11
- 发明人: Michael D. Upton , David J. Sager , Darrell Boggs , Glenn J. Hinton
- 申请人： Michael D. Upton , David J. Sager , Darrell Boggs , Glenn J. Hinton
- 主分类号： G06F900
- IPC分类号： G06F900
摘要：
According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.