Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates. These memory cells are very small in size and provide substantially better programming and erase performance than memory cells of the prior art.