公开(公告)号：US07217621B2

公开(公告)日：2007-05-15

申请号：US11281182

申请日：2005-11-16

Applicant: Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: H01L21/336

CPC classification number: G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract translation: 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20070047298A1

公开(公告)日：2007-03-01

申请号：US11212206

申请日：2005-08-25

Applicant: Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

Inventor： Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines. During an operation of a selected cell, the column decoder selects one of the plurality of column lines, with the one column line selected connected to the first terminal of the selected cell. The first row decoder selects one of the plurality of first row lines with the one first row line selected connected to the second terminal of the selected cell. The second row decoder selects a first plurality of second row lines, with one of the first plurality of second row lines connected to the third terminal of the selected cell. The third row decoder selects a second plurality of third row lines, with one of the second plurality of third row lines connected to the fourth terminal of the selected cell. Finally, the first plurality of second row lines, other than the one second row line, are connected to cells arranged in rows other than rows of cells to which the second plurality of third row lines are connected. The interconnection minimizes programming disturbance.

公开(公告)号：US07037787B2

公开(公告)日：2006-05-02

申请号：US11059475

申请日：2005-02-16

Applicant: Der-Tsyr Fan ,  Jung-Chang Lu ,  Chiou-Feng Chen ,  Prateep Tuntasood

Inventor： Der-Tsyr Fan ,  Jung-Chang Lu ,  Chiou-Feng Chen ,  Prateep Tuntasood

IPC: H01L29/336

CPC classification number: H01L27/115 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Abstract translation: 闪存和制造过程，其中在堆叠的，自对准的浮动和控制栅极之间的沟槽中用选择栅极形成存储器单元，其中由选择栅极选通的掩埋的源极和漏极区域。 擦除路径形成在浮动栅极和选择栅极的突出的圆形边缘之间，并且编程路径从选择栅极之间的中间沟道区域和通过栅极氧化物的浮动栅极延伸到浮动栅极的边缘。 根据阵列结构，可以在浮动和控制栅极的一侧或两侧设置倾斜的选择栅极，并且在蚀刻衬底和其它材料以形成沟槽时将堆叠的栅极和覆盖它们的电介质用作自对准掩模 。

公开(公告)号：US06885586B2

公开(公告)日：2005-04-26

申请号：US10251664

申请日：2002-09-19

Applicant: Chiou-Feng Chen ,  Der-Tsyr Fan ,  Jung-Chang Lu ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Jung-Chang Lu ,  Prateep Tuntasood

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract translation: 自对准分离栅极NAND闪存单元阵列及其制造方法，其中在位线扩散与公共源极扩散之间形成一系列自对准分裂单元。 每个单元具有彼此堆叠和自对准的控制和浮动栅极，以及与另外两个分离而自对准的第三栅极。 在一些公开的实施例中，分裂门用作擦除栅极，而在其它实施例中，它们被用作选择栅极。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20100157687A1

公开(公告)日：2010-06-24

申请号：US12645337

申请日：2009-12-22

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Prateep Tuntasood ,  Der-Tsyr Fan ,  Yaw Wen Hu

IPC: G11C16/06 ,  G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与之绝缘。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US07215573B2

公开(公告)日：2007-05-08

申请号：US11212206

申请日：2005-08-25

Applicant: Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

Inventor： Tseng-Yi Liu ,  Prateep Tuntasood ,  Ben Sheen

IPC: G11C11/34

CPC classification number: G11C16/3418

Abstract: A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines. During an operation of a selected cell, the column decoder selects one of the plurality of column lines, with the one column line selected connected to the first terminal of the selected cell. The first row decoder selects one of the plurality of first row lines with the one first row line selected connected to the second terminal of the selected cell. The second row decoder selects a first plurality of second row lines, with one of the first plurality of second row lines connected to the third terminal of the selected cell. The third row decoder selects a second plurality of third row lines, with one of the second plurality of third row lines connected to the fourth terminal of the selected cell. Finally, the first plurality of second row lines, other than the one second row line, are connected to cells arranged in rows other than rows of cells to which the second plurality of third row lines are connected. The interconnection minimizes programming disturbance.

Abstract translation: 存储器阵列具有以多个行和列布置的多个存储单元。 每个小区至少有四个终端。 阵列具有多条列线，每条列线连接到不同列的单元的第一端。 阵列还具有多个第一行线，其中每条第一行线连接到不同行单元的第二端。 阵列还具有多个第二行线，其中每条第二行线连接到不同行单元的第三端。 最后，该阵列具有多个第三行线，每条第三行线连接到不同行单元格的第四个终端。 列解码器连接到多条列线。 第一行解码器连接到多个第一行行。 第二行解码器连接到多条第二行线。 第三行解码器连接到多个第三行线。 在所选择的单元的操作期间，列解码器选择多条列线中的一条，其中选择一条列线连接到所选择的单元的第一端。 第一行解码器选择多个第一行中的一行，其中选择的一条第一行选择连接到所选择的单元的第二端。 第二行解码器选择第一多个第二行行，其中第一多个第二行行中的一个连接到所选择的单元格的第三个终端。 第三排解码器选择第二多个第三行线，其中第二多个第三行线中的一条连接到所选择的单元的第四端子。 最后，除了一条第二行线之外的第一多个第二行线连接到排列成与第二多个第三行线连接的单元行以外的行的单元。 互连最大限度地减少编程干扰。

公开(公告)号：US20060068529A1

公开(公告)日：2006-03-30

申请号：US11281182

申请日：2005-11-16

Applicant: Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

Inventor： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC: H01L21/8232

CPC classification number: G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

公开(公告)号：US20050145923A1

公开(公告)日：2005-07-07

申请号：US10753103

申请日：2004-01-06

Applicant: Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

Inventor： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC: G11C16/04 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other and

Abstract translation: NAND闪速存储器单元阵列和制造工艺，其中控制栅极和浮置栅极成对地堆叠成排列在位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的门彼此自对齐，并且时，文本丢失或难以辨认

公开(公告)号：US07974136B2

公开(公告)日：2011-07-05

申请号：US12645337

申请日：2009-12-22

Applicant: Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

Inventor： Geeng-Chuan Michael Chern ,  Ben Sheen ,  Jonathan Pabustan ,  Der-Tsyr Fan ,  Yaw Wen Hu ,  Prateep Tuntasood

IPC: G11C16/04

CPC classification number: G11C16/16

Abstract: A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Abstract translation: 闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域 ，在第一端和第二端之间具有通道区域。 闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。 闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。 在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。 此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。 在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

公开(公告)号：US20110057247A1

公开(公告)日：2011-03-10

申请号：US12555756

申请日：2009-09-08

Applicant: Yaw Wen Hu ,  Prateep Tuntasood

Inventor： Yaw Wen Hu ,  Prateep Tuntasood

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7881

Abstract: A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate.

Abstract translation: 非易失性存储单元具有在衬底层上具有第一导电类型的鳍状半导体构件的衬底层。 翅片状构件具有第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，并且在第一区域和第二区域之间延伸的沟道区域。 翅片状构件具有顶表面和在第一区域和第二区域之间的两个侧表面。 字线与第一区域相邻并且电容耦合到沟道区域的第一部分的顶表面和两个侧表面。 浮动栅极与字线相邻并且与顶表面绝缘并且电容耦合到沟道区的第二部分的两个侧表面。 耦合栅极电容耦合到浮动栅极。 擦除栅极与第二区域绝缘并且与浮栅和耦合栅极相邻。