A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.