Invention Grant
- Patent Title: Patterned SOI regions on semiconductor chips
- Patent Title (中): 半导体芯片上的图案化SOI区域
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Application No.: US09975435Application Date: 2001-10-11
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Publication No.: US06756257B2Publication Date: 2004-06-29
- Inventor: Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
- Applicant: Bijan Davari , Devendra Kumar Sadana , Ghavam G. Shahidi , Sandip Tiwari
- Main IPC: H01L2100
- IPC: H01L2100

Abstract:
A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.
Public/Granted literature
- US20030104681A1 Patterned SOI regions on semiconductor chips Public/Granted day:2003-06-05
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