公开(公告)号：US6090689A

公开(公告)日：2000-07-18

申请号：US34445

申请日：1998-03-04

Applicant: Devendra Kumar Sadana ,  Orin Wayne Holland

Inventor： Devendra Kumar Sadana ,  Orin Wayne Holland

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76243

Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Abstract translation: 描述了一种用于形成上绝缘体的方法，其包括以下步骤：在升高的温度下将氧离子注入到硅衬底中，以较低的剂量离子注入低于200℃的氧气以形成非晶硅层;以及 退火步骤以单独形成有缺陷的单晶硅和多晶硅或多晶硅的混合物，然后形成来自非晶硅层的氧化硅，以在硅衬底的表面下方形成连续的氧化硅层，以提供分离的表面硅层。 本发明克服了形成不连续掩埋氧化层的氧化硅的孤立孤岛的问题。

公开(公告)号：US6043166A

公开(公告)日：2000-03-28

申请号：US961131

申请日：1997-10-30

Applicant: Peter Roitman ,  Devendra Kumar Sadana

Inventor： Peter Roitman ,  Devendra Kumar Sadana

IPC: H01L21/265 ,  H01L21/762

CPC classification number: H01L21/26533 ,  H01L21/76243

Abstract: An SOI substrate and method of forming is described incorporating the steps of implanting oxygen under two conditions and performing two high temperature anneals at temperatures above 1250.degree. C. and above 1300.degree. C., respectively, at two respective oxygen concentrations. The invention overcomes the problem of high SOI substrate fabrication cost due to ion implant time and of getting high quality buried oxide (BOX) layers below a thin layer of single crystal silicon.

Abstract translation: 描述SOI衬底和形成方法，其包括在两个条件下注入氧气的步骤，并且在两个相应的氧浓度下分别在高于1250℃和高于1300℃的温度下进行两个高温退火。 本发明克服了由于离子注入时间导致的高SOI衬底制造成本以及在单晶硅薄层之下获得高质量埋藏氧化物（BOX）层的问题。

公开(公告)号：US5930643A

公开(公告)日：1999-07-27

申请号：US995585

申请日：1997-12-22

Applicant: Devendra Kumar Sadana ,  Joel P. de Souza

Inventor： Devendra Kumar Sadana ,  Joel P. de Souza

IPC: H01L21/265 ,  H01L21/762

CPC classification number: H01L21/26533 ,  H01L21/76243

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.

Abstract translation: 利用第一低能量注入步骤在半导体衬底中制造缺陷诱导的掩埋氧化物（DIBOX）区域以产生稳定的缺陷区域的方法; 第二低能量注入步骤，以产生邻近所述稳定缺陷区域的非晶层; 提供氧化和任选的退火。 也提供了包含具有所述DIBOX的所述半导体衬底的绝缘体上硅（SOI）材料。

公开(公告)号：US07550369B2

公开(公告)日：2009-06-23

申请号：US11873928

申请日：2007-10-17

Applicant: Joel Pereira de Souza ,  Keith Edward Fogel ,  John Albrecht Ott ,  Devendra Kumar Sadana ,  Katherine Lynn Saenger

Inventor： Joel Pereira de Souza ,  Keith Edward Fogel ,  John Albrecht Ott ,  Devendra Kumar Sadana ,  Katherine Lynn Saenger

IPC: H01L21/20

CPC classification number: H01L21/26506 ,  H01L21/2022

Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

Abstract translation: 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键部件是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以消除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

公开(公告)号：US07285473B2

公开(公告)日：2007-10-23

申请号：US11031142

申请日：2005-01-07

Applicant: Joel Pereira de Souza ,  Keith Edward Fogel ,  John Albrecht Ott ,  Devendra Kumar Sadana ,  Katherine Lynn Saenger

Inventor： Joel Pereira de Souza ,  Keith Edward Fogel ,  John Albrecht Ott ,  Devendra Kumar Sadana ,  Katherine Lynn Saenger

IPC: H01L21/76

CPC classification number: H01L21/26506 ,  H01L21/2022

Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

Abstract translation: 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

公开(公告)号：US5767549A

公开(公告)日：1998-06-16

申请号：US678442

申请日：1996-07-03

Applicant: Wei Chen ,  Devendra Kumar Sadana ,  Yuan Taur

Inventor： Wei Chen ,  Devendra Kumar Sadana ,  Yuan Taur

IPC: H01L27/12 ,  H01L27/01

CPC classification number: H01L27/1203

Abstract: An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a floating gate due to charge accumulation below the channel of MOS FET's.

Abstract translation: 描述了一种集成电路，其包括衬底，绝缘体层，具有凸起的台面的硅层和薄的区域，以在台面之间提供欧姆导通，台面上的电子器件以及互连布线。 本发明克服了由MOS场效应晶体管下面的电荷累积引起的浮栅问题。

公开(公告)号：US06432754B1

公开(公告)日：2002-08-13

申请号：US09788979

申请日：2001-02-20

Applicant: Fariborz Assaderaghi ,  Tze-Chiang Chen ,  K. Paul Muller ,  Edward Joseph Nowak ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

Inventor： Fariborz Assaderaghi ,  Tze-Chiang Chen ,  K. Paul Muller ,  Edward Joseph Nowak ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

IPC: H01L2100

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618

Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

Abstract translation: 本发明提供了用于形成接地平面SOI器件的各种方法，该器件至少包括形成在绝缘体上硅（SOI）晶片的顶部含Si表面上的场效应晶体管; 以及位于场效应晶体管下方的氧化物区域，位于形成在所述SOI晶片中的源极和漏极区域之间的区域中，所述氧化物区域与所述SOI晶片中形成的浅延伸区对接，并且与所述源极侧向相邻， 漏区。

公开(公告)号：US06333532B1

公开(公告)日：2001-12-25

申请号：US09356295

申请日：1999-07-16

Applicant: Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

Inventor： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC: H01L27108

CPC classification number: H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

Abstract translation: 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度处形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了在形成SOI上的合并逻辑区域的同时形成具有在体Si中的深沟槽的存储电容器形成DRAM的问题。

公开(公告)号：US06300218B1

公开(公告)日：2001-10-09

申请号：US09567095

申请日：2000-05-08

Applicant: Guy Moshe Cohen ,  Devendra Kumar Sadana

Inventor： Guy Moshe Cohen ,  Devendra Kumar Sadana

IPC: H01L2176

CPC classification number: H01L21/76243

Abstract: A method of forming a patterned buried oxide film, includes performing an implantation into a substrate, forming a mask on at least portions of the substrate for controlling the implantation diffusion, and annealing the substrate to form a buried oxide. The mask may be selectively patterned. A region that is covered by the mask has a thinner buried oxide than an area which is exposed directly to the annealing ambient.

Abstract translation: 形成图案化的掩埋氧化膜的方法包括：在衬底中进行注入，在用于控制注入扩散的衬底的至少部分上形成掩模，以及退火衬底以形成掩埋氧化物。 掩模可以被选择性地图案化。 由掩模覆盖的区域比直接暴露于退火环境的区域具有更薄的掩埋氧化物。

公开(公告)号：US07524740B1

公开(公告)日：2009-04-28

申请号：US12108917

申请日：2008-04-24

Applicant: Yaocheng Liu ,  Devendra Kumar Sadana ,  Kern Rim

Inventor： Yaocheng Liu ,  Devendra Kumar Sadana ,  Kern Rim

IPC: H01L21/36 ,  H01L21/20

CPC classification number: H01L29/1054 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/84

Abstract: A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer. The SiGe region and the SPE SiGe region are etched, leaving the relaxed SPE Si region above the buried oxide layer. The nitride pattern is stripped.

Abstract translation: 本发明提供了一种在布置在直接绝缘体（SSDOI）半导体衬底的应变硅中的应变Si层中形成弛豫Si局部区域的方法。 应变Si层形成在设置在Si衬底基底上的掩埋氧化物（BOX）层上。 该方法包括在需要增强的电子迁移率的应变Si层的区域之上沉积氮化物硬掩模图案，在应变Si层内留下未掩模的区域，并执行各种其它处理步骤以修饰和松弛未曝光部分 紧张区域。 该方法包括使用预非晶化注入在未掩模区域上生长EPI SiGe区域，以及在非晶SiGe区域的一部分EPI SiGe区域和非晶Si区域内形成掩埋非晶SiGe区域。 然后，使用SPE再生长，改性非晶SiGe和非晶Si区，实现SPE SiGe区和松弛的SPE Si层。 蚀刻SiGe区域和SPE SiGe区域，在掩埋氧化物层上方留下松弛的SPE Si区域。 剥离氮化物图案。