A CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data. In a CRC code calculation circuit 10 for calculating a CRC code from four-byte parallel data having a residual portion in a final stage, a four-byte parallel CRC code calculation circuit 2calculates a CRC code in parallel from the four-byte parallel data except the final stage. A byte serial conversion circuit 3 converts data of the final stage into serial data. A one-byte serial CRC code calculation circuit 4 calculates a CRC code in serial from the serial data converted by the byte serial conversion circuit 3 using a calculated result of the four-byte parallel CRC code calculation circuit 2 as an initial value.