公开(公告)号：US06829741B1

公开(公告)日：2004-12-07

申请号：US10003029

申请日：2001-10-23

申请人： Masoud Khansari ,  Alireza Abaye

发明人： Masoud Khansari ,  Alireza Abaye

IPC分类号： H03M1300

CPC分类号： H04L1/0083

摘要： Techniques for applying FEC to optical signals such as synchronous transport signal level N SONET frames, as well as other frame structures (e.g., synchronous transport module level N SDH frames) are provided.

摘要翻译： 提供了将FEC应用于诸如同步传输信号级N SONET帧以及其它帧结构（例如，同步传输模块级N SDH帧）的光信号的技术。

公开(公告)号：US06810501B1

公开(公告)日：2004-10-26

申请号：US09752829

申请日：2001-01-03

申请人： Dennis C. Ferguson ,  Devereaux C. Chen ,  Ramesh Padmanabhan ,  Chang-Hong Wu ,  Thomas Michael Skibo

发明人： Dennis C. Ferguson ,  Devereaux C. Chen ,  Ramesh Padmanabhan ,  Chang-Hong Wu ,  Thomas Michael Skibo

IPC分类号： H03M1300

CPC分类号： H03M13/091

摘要： A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one another. The system also receives a signal representing a quantity of valid portions in the data and a current CRC value. The system updates the current CRC value using the data and signal in a single clock cycle.

摘要翻译： 系统更新循环冗余校验（CRC）值。 系统接收包含任意数量的有效和无效部分的数据。 有效部分彼此相邻地定位。 该系统还接收表示数据中有效部分的数量的信号和当前的CRC值。 系统在单个时钟周期内使用数据和信号更新当前CRC值。

公开(公告)号：US06810499B2

公开(公告)日：2004-10-26

申请号：US09874158

申请日：2001-06-04

申请人： Satish Sridharan ,  Michael Jarchi ,  Timothy Coe

发明人： Satish Sridharan ,  Michael Jarchi ,  Timothy Coe

IPC分类号： H03M1300

CPC分类号： H03M13/152 ,  H03M13/29 ,  H03M13/2903 ,  H03M13/2909 ,  H03M13/2927

摘要： A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.

摘要翻译： 多维前向纠错系统。 传输的数据由编码器以多个维度编码。 解码器对接收到的数据的解码在多遍中执行，校正后的数据被重写到存储器中。 一个实施例中的编码器包括并行列解码器和编码（255,239）BCH码的多个行编码器。

公开(公告)号：US06802037B2

公开(公告)日：2004-10-05

申请号：US10028273

申请日：2001-12-28

申请人： Sooyoung Kim ,  Woo-Seok Yang ,  Ho-Jin Lee

发明人： Sooyoung Kim ,  Woo-Seok Yang ,  Ho-Jin Lee

IPC分类号： H03M1300

CPC分类号： H03M13/658 ,  H03M13/152 ,  H03M13/19 ,  H03M13/2963 ,  H03M13/2975 ,  H03M13/4146

摘要： Disclosed is an iterative decoding method using a soft decision output Viterbi algorithm (SOVA) for block turbo codes using product codes wherein block codes are concatenated by greater than three dimensions, which comprises: (a) a transmitter configuring a product code of greater than three dimensions and transmitting it; (b) configuring the signal transmitted by the transmitter into frames for decoding, and initializing external reliability information respectively corresponding to an axis corresponding to the product code of greater than three dimensions; and (c) sequentially iterating the soft decision output Viterbi algorithm (SOVA) decoding with respect to the respective axes.

摘要翻译： 公开了一种迭代解码方法，其使用使用产生代码的块turbo码的软判决输出维特比算法（SOVA），其中块码连接大于三维，其包括：（a）配置大于3的乘积码的发射机 尺寸和传输; （b）将由发射机发送的信号配置成帧以进行解码，以及初始化分别对应于大于三维的乘积码的轴的外部可靠性信息; 和（c）依次迭代相对于各个轴的软判决输出维特比算法（SOVA）解码。

公开(公告)号：US06799295B2

公开(公告)日：2004-09-28

申请号：US10248245

申请日：2002-12-30

申请人： Quang Nguyen

发明人： Quang Nguyen

IPC分类号： H03M1300

CPC分类号： H03M13/3927 ,  H03M13/2771 ,  H03M13/2987 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3961 ,  H03M13/6306 ,  H03M13/6563 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/0055 ,  H04L1/0066 ,  H04L1/0071

摘要： A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing signals from separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the 3rd Generation Wireless system to deliver data rates from up to 2 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP codes. A plurality of parallel Turbo Codes Decoder blocks are provided to compute soft-decoded data RXDa, RXDb from two different receiver path. Several pipelined Log-MAP decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used on the inputted data for pipeline operations. In a pipeline mode, a first decoder A decodes block N data from a first source, while a second decoder B decodes block N data from a second source during the same clock cycle. Pipelined Log-MAP decoders provide high speed data throughput and one output per clock cycle.

摘要翻译： 提供了具有用于从单独的天线计算信号的分集处理的Turbo码解码器的基带处理器。 本发明解码了从建筑物，树木或山丘反射后，经过不同路线到达终端的多径信号。 具有分集处理的Turbo码解码器增加了6dB以上的信噪比（SNR），这使得第3代无线系统能够将数据速率从高达2Mbit / s传输。 本发明提供了几种改进的Turbo码解码器方法和装置，其提供了用于在ASIC或DSP代码中实现Turbo码解码器的更合适，实用和更简单的方法。 提供多个并行Turbo码解码器块以从两个不同的接收机路径计算软解码数据RXDa，RXDb。 几条流水线Log-MAP解码器用于接收数据的迭代解码。 在输入的数据中使用块N数据的滑动窗口进行管道操作。 在流水线模式中，第一解码器A从第一源解码块N数据，而第二解码器B在相同时钟周期期间从第二源解码块N数据。 流水线Log-MAP解码器提供高速数据吞吐量和每个时钟周期一个输出。

公开(公告)号：US06795946B1

公开(公告)日：2004-09-21

申请号：US09565481

申请日：2000-05-05

申请人： Justin A Drummond-Murray ,  Ruben Aszkenasy

发明人： Justin A Drummond-Murray ,  Ruben Aszkenasy

IPC分类号： H03M1300

CPC分类号： H04L1/00

摘要： Apparatus for performing a cyclic redundancy code check on a binary digital signal consisting of a variable multiplicity (M) of data bytes comprises a buffer register for temporarily storing in succession segments each consisting of an integral number (N) of bytes. Each successive segment is loaded into a cyclic redundancy checker which produces a remainder after performing polynomial division of the digital signal. When the number of bytes of the digital signal in the last segment is less than the integral plurality (N) that last segment is padded with constant data. The signal is deemed valid if the remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the checker on a valid digital signal padded with zero to (N−1) bytes of the constant data

摘要翻译： 对由数据字节的可变多项（M）组成的二进制数字信号执行循环冗余码检查的装置包括缓冲寄存器，用于连续地临时存储每个由整数（N）个字节组成的段。 每个连续段被加载到循环冗余校验器中，循环冗余校验器在执行数字信号的多项式除法之后产生余数。 当最后一个段中的数字信号的字节数小于最后一个段用常数数据填充的整数多个（N）时。 如果余数匹配多个预定余数中的任一个，则每个对应于检验器的操作的有效数字信号以0到（N-1）个字节的恒定数据为准，则该信号被认为是有效的

公开(公告)号：US06792569B2

公开(公告)日：2004-09-14

申请号：US09842244

申请日：2001-04-24

申请人： Charles Edwin Cox ,  Martin Aureliano Hassner ,  Barry Marshall Trager ,  Shmuel Winograd

发明人： Charles Edwin Cox ,  Martin Aureliano Hassner ,  Barry Marshall Trager ,  Shmuel Winograd

IPC分类号： H03M1300

CPC分类号： H03M13/1545 ,  H03M13/1515

摘要： An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.

摘要翻译： 纠错代数解码器使用密钥方程求解器来计算六个有限域多项式方程的根，并适用于有效的硬件实现和低延迟方向计算。 解码器通常采用两步法。 第一步是将五次方程转换为性别方程，第二步是采用可逆的Tschirnhausen变换，通过消除5度项来减少性别方程。 Tschirnhausen变换的应用大大降低了将多项式方程转换为矩阵所需的操作的复杂性。 第二步定义了一个特定的高斯消除，将解决五元和多项式多项式方程的问题分解成找到二次方程和四次方程的根的一个更简单的问题。

公开(公告)号：US06763495B2

公开(公告)日：2004-07-13

申请号：US09816513

申请日：2001-03-23

申请人： Masayoshi Suzuki ,  Takao Inoue ,  Kenjiro Mori

发明人： Masayoshi Suzuki ,  Takao Inoue ,  Kenjiro Mori

IPC分类号： H03M1300

CPC分类号： H03M13/091 ,  H03M13/6516

摘要： A CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data. In a CRC code calculation circuit 10 for calculating a CRC code from four-byte parallel data having a residual portion in a final stage, a four-byte parallel CRC code calculation circuit 2calculates a CRC code in parallel from the four-byte parallel data except the final stage. A byte serial conversion circuit 3 converts data of the final stage into serial data. A one-byte serial CRC code calculation circuit 4 calculates a CRC code in serial from the serial data converted by the byte serial conversion circuit 3 using a calculated result of the four-byte parallel CRC code calculation circuit 2 as an initial value.

摘要翻译： 一种用于从作为可变长度数据的字节并行数据计算CRC码的CRC码计算电路。 在用于从具有最后级的残余部分的四字节并行数据中计算CRC码的CRC码计算电路10中，四字节并行CRC码计算电路2从除四字节并行数据之外并行计算CRC码， 最后阶段。 字节串行转换电路3将最后一级的数据转换为串行数据。 一字节串行CRC码计算电路4使用四字节并行CRC码计算电路2的计算结果作为初始值，从由字节串行转换电路3转换的串行数据中串行计算CRC码。

公开(公告)号：US06757864B1

公开(公告)日：2004-06-29

申请号：US09544324

申请日：2000-04-06

申请人： David W. Hansquine

发明人： David W. Hansquine

IPC分类号： H03M1300

CPC分类号： H03M13/4107

摘要： The present invention discloses a method and apparatus for efficiently reading and storing state metrics in memory to enhance high-speed ACS Viterbi decoder implementations. The method includes applying an addressing scheme that determines the address locations of source state metrics during a process cycle. The source state metrics are then read from the address locations during the process cycle and applied to an add-compare-select butterfly operation of a Viterbi algorithm implementation to generate target state metrics. The method then stores each of the target state metrics into the address locations previously occupied by the source state metrics. The method further provides an addressing scheme that determines the address locations of the source state metrics based on a process cycle counter that is incremented and rotated in accordance with the process cycle. The method also provides an addressing scheme that employs a predetermined function to determine the address locations of the source state metrics.

摘要翻译： 本发明公开了一种用于在存储器中高效地读取和存储状态度量以增强高速ACS维特比解码器实现的方法和装置。 该方法包括应用在处理周期期间确定源状态度量的地址位置的寻址方案。 然后在处理周期期间从地址位置读取源状态度量，并将其应用于维特比算法实现的加法比选择蝶形运算以产生目标状态度量。 该方法然后将每个目标状态度量存储在先前由源状态度量占据的地址位置中。 该方法还提供了一种寻址方案，其基于根据处理周期递增和旋转的处理周期计数器来确定源状态度量的地址位置。 该方法还提供了采用预定函数来确定源状态度量的地址位置的寻址方案。

公开(公告)号：US06757861B1

公开(公告)日：2004-06-29

申请号：US09629081

申请日：2000-07-31

申请人： Chuanyou Dong

发明人： Chuanyou Dong

IPC分类号： H03M1300

CPC分类号： G11B20/1833 ,  G11B20/1806 ,  G11B20/1809 ,  G11B20/1866

摘要： Method and system for incdicating that at least one C2 codeword or C1 codeword of a CD data block has an uncorrectable number of errors, by marking or flagging the corrupted symbols of a codeword with defect signals. When a C1 codeword (or C2 codeword) of the data block is found to contain more than a threshold number of errors, a selected number w of distinguishable symbol values (DSVs) is associated with at least one C1 codeword (or with at least one C2 codeword) of the block. When the block is further processed and the presence of more than a threshold number of DSVs is sensed, the system interprets this occurrence as indicating that an uncorrectable group of errors has occurred in a C1 codeword and/or in a C2 codeword of the block.

摘要翻译： 通过用缺陷信号标记或标记已损坏的码字符号，使CD数据块​​的至少一个C2码字或C1码字具有不可校正数量的错误的方法和系统。 当发现数据块的C1码字（或C2码字）包含多于阈值数量的错误时，可选择的可区分码元值（DSV）与至少一个C1码字（或至少一个 C2码字）。 当块被进一步处理并且感测到存在多于阈值数量的DSV时，系统将该事件解释为指示在C1码字和/或该块的C2码字中发生了不可校正的错误组。