Invention Grant
- Patent Title: Electroplating process for avoiding defects in metal features of integrated circuit devices
- Patent Title (中): 用于避免集成电路器件金属特征缺陷的电镀工艺
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Application No.: US09796856Application Date: 2001-02-28
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Publication No.: US06793796B2Publication Date: 2004-09-21
- Inventor: Jonathan D. Reid , David Smith , Steven T. Mayer , Jon Henri , Sesha Varadarajan
- Applicant: Jonathan D. Reid , David Smith , Steven T. Mayer , Jon Henri , Sesha Varadarajan
- Main IPC: C25D518
- IPC: C25D518

Abstract:
Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
Public/Granted literature
- US20010015321A1 Electroplating process for avoiding defects in metal features of integrated circuit devices Public/Granted day:2001-08-23
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