公开(公告)号：US08192806B1

公开(公告)日：2012-06-05

申请号：US12070616

申请日：2008-02-19

Applicant: Sesha Varadarajan ,  Edward Augustyniak ,  Jeffrey Benzing

Inventor： Sesha Varadarajan ,  Edward Augustyniak ,  Jeffrey Benzing

IPC: H05H1/24

CPC classification number: H05H1/46 ,  H01J37/32091 ,  H01J37/32541 ,  H05H2001/4675

Abstract: A plasma-enhanced chemical vapor deposition (PECVD) process including plasma particle extraction is described. Charged particles suspended in discharge volume are moved together with a plasma and can then be flushed away. The particle extraction process reduces unwanted particles on the wafer after deposition and reduces total process time. In some embodiments, the process can involve powering an electrode in the process chamber located away from the wafer. This electrode can be powered up as the main deposition electrode is powered down.

Abstract translation: 描述了包括等离子体粒子提取的等离子体增强化学气相沉积（PECVD）工艺。 悬浮在排出容积中的带电粒子与等离子体一起移动，然后可以被冲走。 颗粒提取过程在沉积后减少晶片上的不需要的颗粒，并减少总处理时间。 在一些实施方案中，该方法可以包括对位于远离晶片的处理室中的电极供电。 当主沉积电极断电时，该电极可以上电。

公开(公告)号：US07745346B2

公开(公告)日：2010-06-29

申请号：US12253807

申请日：2008-10-17

Applicant: Dennis Hausmann ,  James S. Sims ,  Andrew Antonelli ,  Sesha Varadarajan ,  Bart Van Schravendijk

Inventor： Dennis Hausmann ,  James S. Sims ,  Andrew Antonelli ,  Sesha Varadarajan ,  Bart Van Schravendijk

IPC: H01L21/31

CPC classification number: H01L21/31612 ,  C23C16/345 ,  C23C16/402 ,  C23C16/515 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3185

Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.

Abstract translation: 一种使用脉冲等离子体增强化学气相沉积（PECVD）的单次沉积工艺操作在衬底上形成硅基电介质膜的方法，其中等离子体的高频射频功率被脉冲化，从而提高了控制，效率和产品质量 的PECVD过程。 脉冲等离子体的高频RF功率等离子体的高频RF功率降低了每单位时间的沉积膜厚度。 这产生了薄且保形的硅基电介质膜。

公开(公告)号：US20100099271A1

公开(公告)日：2010-04-22

申请号：US12253807

申请日：2008-10-17

Applicant: Dennis Hausmann ,  James S. Sims ,  Andrew Antonelli ,  Sesha Varadarajan ,  Bart Van Schravendijk

Inventor： Dennis Hausmann ,  James S. Sims ,  Andrew Antonelli ,  Sesha Varadarajan ,  Bart Van Schravendijk

IPC: H01L21/314 ,  C23C16/00

CPC classification number: H01L21/31612 ,  C23C16/345 ,  C23C16/402 ,  C23C16/515 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3185

Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.

Abstract translation: 一种使用脉冲等离子体增强化学气相沉积（PECVD）的单次沉积工艺操作在衬底上形成硅基电介质膜的方法，其中等离子体的高频射频功率被脉冲化，从而提高了控制，效率和产品质量 的PECVD过程。 脉冲等离子体的高频RF功率等离子体的高频RF功率降低了每单位时间的沉积膜厚度。 这产生了薄且保形的硅基电介质膜。

公开(公告)号：US08377824B1

公开(公告)日：2013-02-19

申请号：US13437531

申请日：2012-04-02

Applicant: Jonathan Reid ,  Sesha Varadarajan ,  Ugur Emekli

Inventor： Jonathan Reid ,  Sesha Varadarajan ,  Ugur Emekli

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  C25D3/38 ,  C25D5/10 ,  C25D5/50 ,  H01L21/2885 ,  H01L21/76861 ,  H01L21/76873

Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.

Abstract translation: 介绍了在钨上沉积铜的装置和方法。 本发明在半导体工业中特别用于将铜籽晶层沉积到场上或通过具有钨阻挡层的硅通孔，既降低了现有方法的成本和复杂性。

公开(公告)号：US08168540B1

公开(公告)日：2012-05-01

申请号：US12649237

申请日：2009-12-29

Applicant: Jonathan Reid ,  Sesha Varadarajan ,  Ugur Emekli

Inventor： Jonathan Reid ,  Sesha Varadarajan ,  Ugur Emekli

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  C25D3/38 ,  C25D5/10 ,  C25D5/50 ,  H01L21/2885 ,  H01L21/76861 ,  H01L21/76873

Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.

Abstract translation: 介绍了在钨上沉积铜的装置和方法。 本发明在半导体工业中特别用于将铜籽晶层沉积到场上或通过具有钨阻挡层的硅通孔，既降低了现有方法的成本和复杂性。

公开(公告)号：US06884335B2

公开(公告)日：2005-04-26

申请号：US10441607

申请日：2003-05-20

Applicant: Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Sesha Varadarajan ,  Margolita M. Pollack ,  Bryan L. Buckalew ,  Tariq Majid

Inventor： Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Sesha Varadarajan ,  Margolita M. Pollack ,  Bryan L. Buckalew ,  Tariq Majid

IPC: C25D5/04 ,  C25D5/18 ,  C25D7/12 ,  H01L21/288

CPC classification number: C25D5/04 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  Y10S428/935 ,  Y10T428/12993

Abstract: A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.

Abstract translation: 将负偏压施加到浸在电解电镀溶液中的集成电路晶片以产生DC电流。 在第一电镀时间中已经形成最终层厚度的约百分之十到百分之六十之后，在第二电镀时间期间的短暂停期间偏压中断，以产生基本为零的DC电流。 停顿时间为大约2毫秒到5秒，通常为大约10毫秒到500毫秒。 通常，使用约2次暂停至100次暂停，通常约3次暂停至15次停顿。 通常，第二电镀时间期间的直流电流密度大于初始电镀时间期间的直流电流密度。 通常，电镀期间集成电路晶片旋转。 优选地，在第二电镀时间期间，晶片以比第一电镀时间期间更慢的旋转速度旋转。

公开(公告)号：US06793796B2

公开(公告)日：2004-09-21

申请号：US09796856

申请日：2001-02-28

Applicant: Jonathan D. Reid ,  David Smith ,  Steven T. Mayer ,  Jon Henri ,  Sesha Varadarajan

Inventor： Jonathan D. Reid ,  David Smith ,  Steven T. Mayer ,  Jon Henri ,  Sesha Varadarajan

IPC: C25D518

CPC classification number: C25D3/38 ,  C25D5/18 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.

Abstract translation: 使用含有金属离子的电镀浴和抑制剂添加剂，促进剂添加剂和矫光添加剂的电镀方法以及控制施加到基材上的电流密度，避免了具有一定范围的纵横比的特征的基板上的电镀膜的缺陷， 同时提供良好的填充和厚度分布。 这些方法依次包括施加直流阴极电流密度，其优化以在种子层上形成保形薄膜，从而优选地在具有最大纵横比的特征上提供自下而上的填充，并提供所有特征和相邻的特征的保形电镀 场地区域。 在电镀浴中包括流平剂在后续处理后产生更好质量的膜。