发明授权
US06794730B2 High performance PNP bipolar device fully compatible with CMOS process 有权
高性能PNP双极器件完全兼容CMOS工艺

High performance PNP bipolar device fully compatible with CMOS process
摘要:
A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.
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