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US06795369B2 Address buffer and semiconductor memory device using the same 失效
地址缓冲器和使用其的半导体存储器件

Address buffer and semiconductor memory device using the same
Abstract:
The present invention discloses an address buffer and a semiconductor memory device having the address buffer. The address buffer comprises a first buffer for latching a signal in response to a first control signal in a normal operation mode in the semiconductor memory device and generating a buffered signal by buffering the latched signal in response to a second control signal, and a second buffer for maintaining a mode-setting signal in a reset status in the normal operation mode and for outputting the mode-setting signal by using the latched signal in response to the first control signal and a mode-setting command in a mode-setting operation mode. Accordingly, the mode-setting signal is generated only in the mode-setting operation mode, thereby reducing undesirable current consumption.
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