Invention Grant
- Patent Title: Double-layered low dielectric constant dielectric dual damascene method
- Patent Title (中): 双层低介电常数电介质双镶嵌法
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Application No.: US09845480Application Date: 2001-04-30
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Publication No.: US06803314B2Publication Date: 2004-10-12
- Inventor: Shyue Fong Quek , Ting Cheong Ang , Yee Chong Wong , Sang Yee Long
- Applicant: Shyue Fong Quek , Ting Cheong Ang , Yee Chong Wong , Sang Yee Long
- Main IPC: H01L21302
- IPC: H01L21302

Abstract:
A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer. Then, simultaneously, the via pattern is etched into the first dielectric layer and a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings in the fabrication of an integrated circuit device.
Public/Granted literature
- US20020160604A1 Double-layered low dielectric constant dielectric dual damascene method Public/Granted day:2002-10-31
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