公开(公告)号：US06803314B2

公开(公告)日：2004-10-12

申请号：US09845480

申请日：2001-04-30

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76813

摘要： A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer. Then, simultaneously, the via pattern is etched into the first dielectric layer and a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings in the fabrication of an integrated circuit device.

摘要翻译： 描述了双层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 沉积在绝缘层上的第一有机电介质层。 第二无机介电层沉积在第一介电层上。 在第一种方法中，通孔图案被蚀刻到第二介电层中。 使用图案化的第二介电层作为掩模将通孔图案蚀刻到第一介电层中。 此后，将沟槽图案蚀刻到第二无机介电层中以完成双镶嵌开口。 在第二种方法中，沟槽图案被蚀刻到第二介电层中。 此后，通过第二无机介电层和第一有机介电层蚀刻通孔图案以完成双镶嵌开口。 在第三种方法中，通孔图案被蚀刻到第二介电层中。 然后，同时，通孔图案被蚀刻到第一介电层中，并且沟槽图案被蚀刻到第二无机介电层中，以在集成电路器件的制造中完成双镶嵌开口。

公开(公告)号：US06406994B1

公开(公告)日：2002-06-18

申请号：US09726657

申请日：2000-11-30

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

IPC分类号： H01L2144

CPC分类号： B41M5/5254 ,  B41M5/508 ,  B41M5/5218 ,  B41M5/5272 ,  Y10T428/24802

摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.

摘要翻译： 描述了三层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 第一类型的第一介电层沉积在绝缘层上。 第二类型的第二介电层沉积在第一介电层上。 通孔图案被蚀刻到第二介电层中。 此后，第一类型的第三电介质层沉积在图案化的第二介电层上。 同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。 如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。 如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。