发明授权
US06809037B2 MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING SIMULTANEOUS FORMATION OF VIA-HOLE REACHING METAL WIRING AND CONCAVE GROOVE IN INTERLAYER FILM AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED WITH THE MANUFACTURING METHOD
有权
半导体集成电路的制造方法，包括同时形成通过制造方法制造的中间层膜和半导体集成电路中的金属接线和凹槽的同时形成的方法
- 专利标题： MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING SIMULTANEOUS FORMATION OF VIA-HOLE REACHING METAL WIRING AND CONCAVE GROOVE IN INTERLAYER FILM AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED WITH THE MANUFACTURING METHOD
- 专利标题（中）： 半导体集成电路的制造方法，包括同时形成通过制造方法制造的中间层膜和半导体集成电路中的金属接线和凹槽的同时形成的方法
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申请号： US09751979申请日： 2000-12-29
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公开(公告)号： US06809037B2公开(公告)日： 2004-10-26
- 发明人: Atsushi Nishizawa
- 申请人： Atsushi Nishizawa
- 优先权： JP2000-009221 20000118
- 主分类号： H01L21302
- IPC分类号： H01L21302
摘要：
The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole reaching a metal wiring and a concave groove are simultaneously formed in an interlayer film. When the interlayer film and the material of an organic film embedded in the via hole are etched, the etching rate for the material of the organic film with an etching gas is set to be higher than the etching rate for the interlayer film with an etching gas. Thus, plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of the concave groove formed in the interlayer film, and the production of depositions is prevented.