发明授权
- 专利标题: Logic circuit design equipment and method for designing logic circuit for reducing leakage current
- 专利标题(中): 逻辑电路设计和设计用于减少漏电流逻辑电路的方法
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申请号: US10114159申请日: 2002-04-01
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公开(公告)号: US06813750B2公开(公告)日: 2004-11-02
- 发明人: Kimiyoshi Usami , Naoyuki Kawabe , Takeshi Kitahara , Masahiro Kanazawa
- 申请人: Kimiyoshi Usami , Naoyuki Kawabe , Takeshi Kitahara , Masahiro Kanazawa
- 优先权: JPP2001-103695 20010402
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.