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    Logic circuit design equipment and method for designing logic circuit for reducing leakage current
    3.
    发明授权
    Logic circuit design equipment and method for designing logic circuit for reducing leakage current 失效
    逻辑电路设计和设计用于减少漏电流逻辑电路的方法

    公开(公告)号：US06813750B2

    公开(公告)日：2004-11-02

    申请号：US10114159

    申请日：2002-04-01

    申请人： Kimiyoshi Usami ,  Naoyuki Kawabe ,  Takeshi Kitahara ,  Masahiro Kanazawa

    发明人： Kimiyoshi Usami ,  Naoyuki Kawabe ,  Takeshi Kitahara ,  Masahiro Kanazawa

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

    摘要翻译： 逻辑电路设计设备和逻辑电路设计方法包括分析所有第一单元的输入状态，分析在每个第一单元是高Vth单元的情况下所有第一单元的泄漏电流，其中低Vth单元在低电平下显示小的漏电流 分别在高速运转时显示大的漏电流的低Vth电池，并且在满足定时限制的范围内将第一单元替换为第二单元。 这里，第二小区的阈值与第一小区的阈值不同。

    Semiconductor integrated circuit, logic operation circuit, and flip flop
    4.
    发明授权
    Semiconductor integrated circuit, logic operation circuit, and flip flop 失效
    半导体集成电路，逻辑运算电路和触发器

    公开(公告)号：US06750680B2

    公开(公告)日：2004-06-15

    申请号：US09883959

    申请日：2001-06-20

    申请人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

    发明人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

    IPC分类号： H03K19096

    CPC分类号： H03K19/01707 ,  H03K19/0016

    摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

    摘要翻译： 提供了能够高速运行并且具有泄漏电流降低的半导体集成电路，逻辑运算电路和触发器。在根据本发明的半导体集成电路中，仅在关键路径上的门电路 由具有低阈值电压的晶体管与具有高阈值电压的晶体管组合而获得的MT门单元构成，并且任何其它门电路由具有高阈值电压的晶体管构成。 因此，关键路径上的门电路可以高速运转，能够抑制整体的漏电流，从而降低功耗。

    Multi-power supply integrated circuit and system employing the same
    6.
    发明授权
    Multi-power supply integrated circuit and system employing the same 失效
    多电源集成电路及采用该电路的系统

    公开(公告)号：US5920089A

    公开(公告)日：1999-07-06

    申请号：US882082

    申请日：1997-06-25

    申请人： Masahiro Kanazawa ,  Kimiyoshi Usami

    发明人： Masahiro Kanazawa ,  Kimiyoshi Usami

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/118 ,  H03K19/00 ,  H01L29/76

    CPC分类号： H01L27/088 ,  H01L27/11807

    摘要： There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

    摘要翻译： 公开了一种多电源集成电路，其包括形成在第一n阱中并在第一电源电压下操作的第一pMOS晶体管和形成在第二n阱中的第二pMOS晶体管，并在第二n沟道中操作 电源电压低于第一电源电压，其中第一n阱和第二n阱相邻放置以在其间设置边界线，并且第一电源电压被提供给第一和第二n阱。 因为第一和第二n阱之间的空间变小，所以提供了具有减小的芯片面积的栅阵列LSI。 可以形成常见的n阱来代替第一和第二n阱。