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    POWER CONSUMPTION ANALYZING APPARATUS AND POWER CONSUMPTION ANALYZING METHOD
    1.
    发明申请
    POWER CONSUMPTION ANALYZING APPARATUS AND POWER CONSUMPTION ANALYZING METHOD 有权
    消耗电力分析仪器和功耗分析方法

    公开(公告)号：US20090006012A1

    公开(公告)日：2009-01-01

    申请号：US12142073

    申请日：2008-06-19

    申请人： Naoyuki Kawabe

    发明人： Naoyuki Kawabe

    IPC分类号： G01R21/00 ,  G06F11/30

    CPC分类号： G06F17/5022

    摘要： A power consumption analyzing apparatus has a clock gating cell detector configured to detect a clock gating cell which is not present in RTL data but present in a gate-level netlist based on the RTL data of a target circuit and the netlist corresponding to the RTL data, a test bench description generation unit configured to add a description concerning the clock gating cell detected by the clock gating cell detector to the RTL data, a monitor signal generation unit configured to specify a monitor signal used for power consumption analysis from the RTL data obtained by adding the description concerning the clock gating cell, an RTL simulation unit configured to execute operational simulation of the target circuit by using the RTL data obtained by adding the description concerning the clock gating cell, a monitor unit configured to detect a logic of the monitor signal during the execution of the operational simulation, and a power consumption analysis unit configured to analyze power consumption due to a toggle at a clock terminal of the clock synchronizing cell included in the target circuit.

    摘要翻译： 功耗分析装置具有：时钟门控单元检测器，被配置为基于目标电路的RTL数据和对应于RTL数据的网表来检测RTL数据中不存在但存在于门级网表中的时钟门控单元 测试台描述生成单元，被配置为将关于由时钟门控单元检测器检测到的时钟门控单元的描述添加到RTL数据;监视信号生成单元，被配置为从获得的RTL数据中指定用于功耗分析的监视信号 通过添加关于时钟选通单元的描述，将RTL模拟单元配置为通过使用通过添加关于时钟门控单元的描述而获得的RTL数据来执行目标电路的操作模拟;监视单元，被配置为检测监视器的逻辑 信号，以及功率分析单元，被配置为分析功率共享 由于在目标电路中包括的时钟同步单元的时钟端子处的切换引起的消耗。

    Power supply wiring structure
    3.
    发明授权
    Power supply wiring structure 有权
    电源接线结构

    公开(公告)号：US08751992B2

    公开(公告)日：2014-06-10

    申请号：US13420945

    申请日：2012-03-15

    申请人： Tetsuaki Utsumi ,  Naoyuki Kawabe ,  Keiji Omotani

    发明人： Tetsuaki Utsumi ,  Naoyuki Kawabe ,  Keiji Omotani

    IPC分类号： G06F17/50 ,  H01L23/52

    CPC分类号： G11C5/063

    摘要： According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.

    摘要翻译： 根据实施例，提供了包括沿第一方向延伸的第一和第二下层电源线以及沿第二方向延伸的第一和第二上层电源线的半导体集成电路。 上层电源线和下层电源线之间的第一和第二连接线沿着第二方向布置在同一条线上。 从连接线延伸出来的第一和第二位置转换线布置在第一和第二连接线之间。 设置在位置转换线上的第一和第二上侧通孔沿着第一方向布置在同一条线上。

    Power consumption analyzing apparatus and power consumption analyzing method
    4.
    发明授权
    Power consumption analyzing apparatus and power consumption analyzing method 有权
    功耗分析仪和功耗分析方法

    公开(公告)号：US07908100B2

    公开(公告)日：2011-03-15

    申请号：US12142073

    申请日：2008-06-19

    申请人： Naoyuki Kawabe

    发明人： Naoyuki Kawabe

    IPC分类号： G01R31/00

    CPC分类号： G06F17/5022

    摘要： A power consumption analyzing apparatus has a clock gating cell detector configured to detect a clock gating cell which is not present in RTL data but present in a gate-level netlist, a test bench description generation unit configured to add a description concerning the clock gating cell, a monitor signal generation unit configured to specify a monitor signal used for power consumption analysis from the RTL data, an RTL simulation unit configured to execute operational simulation of the target circuit, a monitor unit configured to detect a logic of the monitor signal during the execution of the operational simulation, and a power consumption analysis unit configured to analyze power consumption.

    摘要翻译： 功耗分析装置具有：时钟门控单元检测器，被配置为检测RTL数据中不存在但存在于门级网表中的时钟门控单元;测试台描述生成单元，被配置为添加关于时钟门控单元的描述 ，配置为从所述RTL数据指定用于功耗分析的监视信号的监视信号生成单元，被配置为执行所述目标电路的操作模拟的RTL模拟单元，被配置为在所述目标电路期间检测所述监视信号的逻辑的监视单元 执行操作模拟，以及功耗分析单元，被配置为分析功耗。

    DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM
    9.
    发明申请
    DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM 审中-公开
    设计设计，设计方法和计算机可读介质

    公开(公告)号：US20110191734A1

    公开(公告)日：2011-08-04

    申请号：US12887044

    申请日：2010-09-21

    申请人： Jiro HAYAKAWA ,  Naoyuki KAWABE ,  Hiroshige ORITA ,  Takashi BAN

    发明人： Jiro HAYAKAWA ,  Naoyuki KAWABE ,  Hiroshige ORITA ,  Takashi BAN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： In general, according to one embodiment, a designing apparatus includes a clock tree generator, a logic modifier, a layout modifier, and an outputting module. The clock tree generator is configured to generate a clock tree. The logic modifier is configured to logically insert a delay element in such a manner that a hold violation is modified without considering a setup timing with respect to circuit data corresponding to the clock tree generated by the clock tree generator. The layout modifier is configured to modify a layout of a semiconductor integrated circuit based on a processing result of the logic modifier. The outputting module is configured to output the layout of the semiconductor integrated circuit. The layout is modified by the layout modifier.

    摘要翻译： 通常，根据一个实施例，设计装置包括时钟树生成器，逻辑修改器，布局修改器和输出模块。 时钟树生成器被配置为生成时钟树。 逻辑修改器被配置为逻辑地插入延迟元件，使得在不考虑与由时钟树生成器生成的时钟树相对应的电路数据的设置定时的情况下修改保持违例。 布局修改器被配置为基于逻辑修改器的处理结果来修改半导体集成电路的布局。 输出模块被配置为输出半导体集成电路的布局。 布局由布局修改器修改。