In an image processing circuit, a color correction section, an area determination section and a MTF correction section each comprises a rewritable device (for example, field programmable gate array (FPGA) circuit) including a plurality of line memories (FIFO memories). A CPU reconstructs the image processing function of the FPGA circuit by using setting information and a processing program stored in the ROM in accordance with the set image processing condition such as the processing speed priority mode or the image quality priority mode.