发明授权
- 专利标题: Cell circuit for multiport memory using decoder
- 专利标题(中): 使用解码器的多端口存储器的单元电路
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申请号: US10273567申请日: 2002-10-17
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公开(公告)号: US06826110B2公开(公告)日: 2004-11-30
- 发明人: Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
- 申请人: Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
- 主分类号: G11C800
- IPC分类号: G11C800
摘要:
An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.
公开/授权文献
- US20040076063A1 Cell circuit for multiport memory using decoder 公开/授权日:2004-04-22
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