Invention Grant
US06828161B2 Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
有权
形成具有多层硬掩模并构图的FeRAM的方法
- Patent Title: Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
- Patent Title (中): 形成具有多层硬掩模并构图的FeRAM的方法
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Application No.: US10313068Application Date: 2002-12-06
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Publication No.: US06828161B2Publication Date: 2004-12-07
- Inventor: Scott R. Summerfelt , Sanjeev Aggarwal , Luigi Colombo , Theodore S. Moise, IV , J. Scott Martin
- Applicant: Scott R. Summerfelt , Sanjeev Aggarwal , Luigi Colombo , Theodore S. Moise, IV , J. Scott Martin
- Main IPC: H01L2100
- IPC: H01L2100

Abstract:
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.
Public/Granted literature
- US20030124748A1 Method of forming an FeRAM having a multi-layer hard mask and patterning thereof Public/Granted day:2003-07-03
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