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    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
    1.
    发明授权
    Method of forming an FeRAM having a multi-layer hard mask and patterning thereof 有权
    形成具有多层硬掩模并构图的FeRAM的方法

    公开(公告)号：US06828161B2

    公开(公告)日：2004-12-07

    申请号：US10313068

    申请日：2002-12-06

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。

    Method of fabricating a ferroelectric memory cell
    7.
    发明授权
    Method of fabricating a ferroelectric memory cell 有权
    制造铁电存储单元的方法

    公开(公告)号：US06548343B1

    公开(公告)日：2003-04-15

    申请号：US09702985

    申请日：2000-10-31

    申请人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    发明人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    IPC分类号： H01L218242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

    摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

    摘要翻译： 本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面 和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤 形成阻挡层的步骤。

    Hardmask designs for dry etching FeRAM capacitor stacks
    9.
    发明授权
    Hardmask designs for dry etching FeRAM capacitor stacks 有权
    硬掩模设计用于干蚀刻FeRAM电容器堆叠

    公开(公告)号：US06534809B2

    公开(公告)日：2003-03-18

    申请号：US09741479

    申请日：2000-12-19

    申请人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    发明人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    IPC分类号： H01L2994

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

    摘要： An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

    摘要翻译： 本发明的一个实施方案是形成在半导体衬底上的铁电电容器，所述铁电电容器包括：形成在所述半导体衬底上的底部电极，所述底部电极由底部电极材料（图4a的304）组成; 形成在底部电极上并由第一电极材料（图4a的306和308）组成的顶部电极; 位于顶部电极和底部电极之间的铁电材料（图4a的306） 以及形成在顶部电极上并包括底部硬掩模层（图4a的402）和形成在底部硬掩模层上的顶部硬掩模层（图4a的408）的硬掩模，所述顶部硬掩模层能够使用支架蚀刻剂 蚀刻底部电极，顶部电极和铁电材料以使蚀刻期间底部硬掩模层基本上不被去除，并且底部硬掩模层由基本上充当氢扩散阻挡层的导电材料构成。

    Metal patterning with adhesive hardmask layer
    10.
    发明授权
    Metal patterning with adhesive hardmask layer 失效
    金属图案与粘合剂硬掩模层

    公开(公告)号：US06211034B1

    公开(公告)日：2001-04-03

    申请号：US09059546

    申请日：1998-04-13

    申请人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

    发明人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

    IPC分类号： H01L218242

    CPC分类号： H01L28/60 ,  H01L21/32139 ,  H01L27/1085

    摘要： An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.

    摘要翻译： 一种粘附硬掩模结构和蚀刻存储器件电容器结构中的底部电极的方法，其在底部电极的蚀刻期间省去了对任何粘附促进剂的需要。 通过使用氮化硅作为硬掩模220，简化了处理，并且可以产生更坚固的电容器结构。 与通过任何方法形成的氧化硅相比，已经显示氮化硅220产生显着增强的与铂210的粘合性。 由于氮化硅220是抗氧化的，所以它有利地抵抗可能在蚀刻化学中使用的任何氧等离子体。 这种蚀刻工艺可以在> = 256Mbit的DRAM中的高k电容器结构的处理期间使用。