- 专利标题: Vertical nanotube transistor and process for fabricating the same
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申请号: US10301715申请日: 2002-11-22
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公开(公告)号: US06830981B2公开(公告)日: 2004-12-14
- 发明人: Chun-Tao Lee , Lin-Hung Shi , Chi-Cherng Jeng , Wen-Ti Lin , Wei-Su Chen
- 申请人: Chun-Tao Lee , Lin-Hung Shi , Chi-Cherng Jeng , Wen-Ti Lin , Wei-Su Chen
- 优先权: TW91114596A 20020702
- 主分类号: H01L21331
- IPC分类号: H01L21331
摘要:
A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.
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