发明授权
US06830982B1 Method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor
有权
降低外部碱性电阻并提高NPN晶体管可制造性的方法
- 专利标题: Method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor
- 专利标题(中): 降低外部碱性电阻并提高NPN晶体管可制造性的方法
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申请号: US10290976申请日: 2002-11-07
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公开(公告)号: US06830982B1公开(公告)日: 2004-12-14
- 发明人: David Howard , Marco Racanelli , Greg D. U'Ren
- 申请人: David Howard , Marco Racanelli , Greg D. U'Ren
- 主分类号: H01L21331
- IPC分类号: H01L21331
摘要:
According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
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