发明授权
US06831329B2 Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off
失效
通过具有栅极可控DI / DT的IGBT快速触发,并在感应关断时降低EMI
- 专利标题: Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off
- 专利标题(中): 通过具有栅极可控DI / DT的IGBT快速触发,并在感应关断时降低EMI
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申请号: US10278224申请日: 2002-10-22
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公开(公告)号: US06831329B2公开(公告)日: 2004-12-14
- 发明人: Joseph A. Yedinak , Jon Gladish , Sampat Shekhawat , Gary M. Dolny , Praveen Muraleedharan Shenoy , Douglas Joseph Lange , Mark L. Rinehimer
- 申请人: Joseph A. Yedinak , Jon Gladish , Sampat Shekhawat , Gary M. Dolny , Praveen Muraleedharan Shenoy , Douglas Joseph Lange , Mark L. Rinehimer
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.