Invention Grant
US06842130B2 Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
失效
在Σ-ΔDAC中实现动态元件匹配的高效实现
- Patent Title: Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
- Patent Title (中): 在Σ-ΔDAC中实现动态元件匹配的高效实现
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Application No.: US10812975Application Date: 2004-03-31
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Publication No.: US06842130B2Publication Date: 2005-01-11
- Inventor: Minsheng Wang , Anil Tammineedi
- Applicant: Minsheng Wang , Anil Tammineedi
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F7/76
- IPC: G06F7/76 ; H03M1/06 ; H03M3/04 ; H03M3/00

Abstract:
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ∀1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
Public/Granted literature
- US20040178939A1 Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's Public/Granted day:2004-09-16
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