- 专利标题： Method for semiconductor gate line dimension reduction
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申请号： US10334337申请日： 2002-12-30
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公开(公告)号： US06849530B2公开(公告)日： 2005-02-01
- 发明人: Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
- 申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
- 申请人地址： US CA Sunnyvale
- 专利权人： Advanced Micro Devices
- 当前专利权人： Advanced Micro Devices
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Foley & Lardner LLP
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/4763
摘要：
To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
公开/授权文献
- US20040043590A1 Method for semiconductor gate line dimension reduction 公开/授权日：2004-03-04
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