公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US07268066B2

公开(公告)日：2007-09-11

申请号：US10922093

申请日：2004-08-19

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/4763

CPC分类号： H01L29/66477 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

公开(公告)号：US06849530B2

公开(公告)日：2005-02-01

申请号：US10334337

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/28 ,  H01L21/4763

CPC分类号： H01L21/28123

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US06764947B1

公开(公告)日：2004-07-20

申请号：US10366801

申请日：2003-02-14

申请人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

发明人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

IPC分类号： H01L214763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

摘要翻译： 在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。 应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。 应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。 在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

公开(公告)号：US06825114B1

公开(公告)日：2004-11-30

申请号：US10424675

申请日：2003-04-28

申请人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。

公开(公告)号：US06884733B1

公开(公告)日：2005-04-26

申请号：US10215173

申请日：2002-08-08

申请人： Srikanteswara Dakshina-Murthy ,  Scott A. Bell ,  David E. Brown ,  Philip A. Fisher

发明人： Srikanteswara Dakshina-Murthy ,  Scott A. Bell ,  David E. Brown ,  Philip A. Fisher

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28123

摘要： A method of producing an integrated circuit eliminates the need to re-oxidize polysilicon gate conductors and lines prior to removal of a hard mask used to form the gate conductors. A layer of polysilicon is provided above a semiconductor substrate. The layer of polysilicon is then doped. A mask material comprising amorphous carbon is provided above the layer of polysilicon, and the layer of mask material is patterned to form a mask. A portion of the layer of polysilicon is removed according to the mask, and the mask is removed.

摘要翻译： 制造集成电路的方法消除了在去除用于形成栅极导体的硬掩模之前再次氧化多晶硅栅极导体和线的需要。 在半导体衬底之上设置多晶硅层。 然后掺杂多晶硅层。 包含无定形碳的掩模材料设置在多晶硅层上方，并且掩模材料层被图案化以形成掩模。 根据掩模去除多晶硅层的一部分，并且去除掩模。

公开(公告)号：US20120007221A1

公开(公告)日：2012-01-12

申请号：US13241810

申请日：2011-09-23

申请人： Richard J. Huang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery ,  Lu You

发明人： Richard J. Huang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery ,  Lu You

IPC分类号： H01L29/66 ,  C23F1/00

CPC分类号： H01L21/28123 ,  H01L21/0332 ,  H01L21/28035 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

摘要翻译： 形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。 掩模材料包括无定形碳。 该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。 根据掩模在导电材料层中形成特征。

公开(公告)号：US07521304B1

公开(公告)日：2009-04-21

申请号：US10230775

申请日：2002-08-29

申请人： Richard J. Huang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery ,  Lu You

发明人： Richard J. Huang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery ,  Lu You

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L21/0332 ,  H01L21/28035 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

摘要翻译： 形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。 掩模材料包括无定形碳。 该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。 根据掩模在导电材料层中形成特征。

公开(公告)号：US08629535B2

公开(公告)日：2014-01-14

申请号：US13241810

申请日：2011-09-23

申请人： Richard J. Huang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery ,  Lu You

发明人： Richard J. Huang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Richard C. Nguyen ,  Cyrus E. Tabery ,  Lu You

IPC分类号： H01L23/58

CPC分类号： H01L21/28123 ,  H01L21/0332 ,  H01L21/28035 ,  H01L21/32139 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

摘要翻译： 形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。 掩模材料包括无定形碳。 该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。 根据掩模在导电材料层中形成特征。