发明授权
- 专利标题: Phase-lock loop having programmable bandwidth
- 专利标题(中): 具有可编程带宽的锁相环
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申请号: US10264360申请日: 2002-10-04
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公开(公告)号: US06853252B2公开(公告)日: 2005-02-08
- 发明人: Mark Dickmann
- 申请人: Mark Dickmann
- 申请人地址: US FL Palm, Bay
- 专利权人: Intersil Corporation
- 当前专利权人: Intersil Corporation
- 当前专利权人地址: US FL Palm, Bay
- 代理机构: Graybeal Jackson Haley LLP
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; G06F1/26 ; H03K5/00 ; H03K23/66 ; H03L7/07 ; H03L7/089 ; H03L7/107 ; H03L7/183 ; H03L7/00
摘要:
A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal. The PLL further comprises a phase-frequency detector (PFD) coupled to the oscillator and operable to receive a reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal derived from the oscillator signal. The PLL further comprises an error-correction signal suppression circuit coupled to the PFD and operable to control the loop bandwidth of the PLL by periodically enabling the PFD.
公开/授权文献
- US20040066238A1 Phase-lock loop having programmable bandwidth 公开/授权日:2004-04-08
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